EP2A25F672C7N vs EP2A25F672I6 Comparison
Detailed side-by-side comparison of EP2A25F672C7N by Altera and EP2A25F672I6 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672C7N | EP2A25F672I6 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $195.00 | $178.00 |
| Family | APEX II | APEX II |
| Logic Elements | 24,320 cells | β |
| System Gates | Approximately 900,000 | β |
| User I/Os | 492 | β |
| Propagation Delay (tPD) | 1.69 ns | β |
| Internal Operating Frequency | Up to 500 MHz | β |
| Core Voltage (VCCINT) | 1.5 V | β |
| Process Technology | 0.15 Β΅m all-layer copper (up to 8 metal layers) | 0.18 Β΅m CMOS |
| Logic Family | CMOS | β |
| Package Type | 672-ball FC-FBGA (FineLine BGA) | β |
| Package Body Size | 27 x 27 mm | β |
| Ball Pitch | 1.0 mm | β |
| Operating Temperature | 0 Β°C to 85 Β°C (commercial) | β |
| High-Speed I/O Support | True-LVDS, LVPECL, PCML, HyperTransport up to 1 Gbps | β |
| Programmable Logic Type | Loadable PLD (in-system programmable) | β |
| Embedded Memory | Embedded System Blocks (ESB) configurable as dual-port RAM/ROM | Embedded System Blocks (ESB), dual-port RAM / CAM |
| PLLs | Up to 4 | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Logic Elements (typical gates) | β | 25,000 |
| Fabric Architecture | β | SRAM-based LUT |
| Package | β | 672-ball FineLine BGA (FBGA-672) |
| Core Voltage | β | 1.5 V |
| Configuration Method | β | External SRAM configuration device (EPC series) |
| Temperature Grade | β | Industrial (-40 Β°C to +100 Β°C ambient) |
| Speed Grade | β | 6 |
| DSP Blocks | β | MultiCore dedicated multipliers |
| Boundary Scan | β | JTAG (IEEE 1149.1) compliant |
| Clock Management | β | Dedicated PLL / clock tree circuitry |
| I/O Bank Count | β | [DATA_NEEDED: number of user I/O banks] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| MSL Level | β | [DATA_NEEDED: moisture sensitivity level] |