EP2A25F672C9 vs EP2A25F672ES Comparison
Detailed side-by-side comparison of EP2A25F672C9 by Altera and EP2A25F672ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672C9 | EP2A25F672ES |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $700.00 | $198.00 |
| Family | APEX II | APEX II |
| Logic Elements (LE) | Approximately 25,000 | β |
| Macro Cells | 2432 | β |
| User I/O | 492 | β |
| Package | 672-ball FCBGA (FineLine BGA) | 672-ball FC-FBGA |
| Package Dimensions | 27 mm x 27 mm | β |
| Ball Pitch | 1.0 mm | β |
| Process Technology | 0.15 Β΅m all-layer copper, up to 8 metal layers | 0.15 Β΅m CMOS |
| Logic Family | CMOS | β |
| Propagation Delay | 1.69 ns | β |
| Operating Temperature | 0Β°C to 85Β°C (Commercial) | β |
| Supply Voltage | [DATA_NEEDED: core VCC voltage] | β |
| I/O Standards | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) | β |
| Configuration | Passive Serial, Passive Parallel Synchronous, JTAG | β |
| Embedded Memory | ESBs for dual-port RAM, ROM, FIFO | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED] | Compliant |
| Logic Elements | β | 24,320 |
| Maximum Gates | β | 900,000 |
| Embedded System Blocks (ESBs) | β | 24 |
| Maximum Embedded RAM | β | 1.4 Mbit |
| Maximum User I/O Pins | β | 492 |
| Core Voltage | β | 1.5 V |
| Maximum System Clock Frequency | β | 500 MHz |
| Number of PLLs | β | 4 |
| I/O Banks | β | 16 |
| Supported I/O Standards | β | LVTTL, LVCMOS, PCI, LVDS, LVPECL, HSTL |
| Configuration Mode | β | Serial / Parallel / JTAG |
| Operating Temperature Range | β | [DATA_NEEDED: operating temperature range] |