EP2A25F672C9 vs EP2A25F672I6 Comparison

Detailed side-by-side comparison of EP2A25F672C9 by Altera and EP2A25F672I6 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP2A25F672C9 EP2A25F672I6
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $700.00 $178.00
Family APEX II APEX II
Logic Elements (LE) Approximately 25,000 β€”
Macro Cells 2432 β€”
User I/O 492 β€”
Package 672-ball FCBGA (FineLine BGA) 672-ball FineLine BGA (FBGA-672)
Package Dimensions 27 mm x 27 mm β€”
Ball Pitch 1.0 mm β€”
Process Technology 0.15 Β΅m all-layer copper, up to 8 metal layers 0.18 Β΅m CMOS
Logic Family CMOS β€”
Propagation Delay 1.69 ns β€”
Operating Temperature 0Β°C to 85Β°C (Commercial) β€”
Supply Voltage [DATA_NEEDED: core VCC voltage] β€”
I/O Standards LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) β€”
Configuration Passive Serial, Passive Parallel Synchronous, JTAG β€”
Embedded Memory ESBs for dual-port RAM, ROM, FIFO Embedded System Blocks (ESB), dual-port RAM / CAM
Mounting Type Surface Mount Surface Mount (BGA)
RoHS Status [DATA_NEEDED] [DATA_NEEDED: RoHS compliance status]
Logic Elements (typical gates) β€” 25,000
Fabric Architecture β€” SRAM-based LUT
Core Voltage β€” 1.5 V
Configuration Method β€” External SRAM configuration device (EPC series)
Temperature Grade β€” Industrial (-40 Β°C to +100 Β°C ambient)
Speed Grade β€” 6
DSP Blocks β€” MultiCore dedicated multipliers
Boundary Scan β€” JTAG (IEEE 1149.1) compliant
Clock Management β€” Dedicated PLL / clock tree circuitry
I/O Bank Count β€” [DATA_NEEDED: number of user I/O banks]
Lead-Free β€” [DATA_NEEDED: lead-free status]
MSL Level β€” [DATA_NEEDED: moisture sensitivity level]

Datasheets & Resources

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