EP2A25F672I9N vs EP2A25F672I-9 Comparison
Detailed side-by-side comparison of EP2A25F672I9N by Intel and EP2A25F672I-9 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A25F672I9N | EP2A25F672I-9 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $215.00 | $195.00 |
| Series | APEX II (EP2A25) | β |
| Family | APEX II | APEX II |
| Device Type | FPGA (Field-Programmable Gate Array) | β |
| Logic Elements / Cells | 24,320 | β |
| System Gates | 900,000 (typical) | β |
| Process Technology | 0.15 Β΅m CMOS | 0.18 Β΅m CMOS |
| Maximum Internal Frequency | 236 MHz | β |
| Propagation Delay (tpd) | 2.23 ns | β |
| Core Supply Voltage (VCCINT) | 1.5 V nominal (1.425 V to 1.525 V) | β |
| I/O Supply Voltage | [DATA_NEEDED: VCCIO range] | β |
| Package | 672-pin FC-FBGA | 672-pin FCBGA (FineLine BGA) |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Operating Temperature | -40 Β°C to +85 Β°C (Industrial, 'I' suffix) | β |
| Speed Grade | 9 (fastest commercial APEX II) | -9 |
| Embedded System Blocks (ESB) | Yes (on-chip RAM/ROM) | β |
| PLLs | 4 | β |
| Configuration | JTAG / in-system programmable | β |
| RoHS Status | [DATA_NEEDED: confirmed] | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED] | β |
| AEC-Q100 | not_applicable | β |
| Logic Elements (typical) | β | 25,000 |
| Maximum System Gates | β | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESB) Memory | β | 1,125 Kbits |
| Maximum User I/O Pins | β | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | β | 4 |
| Core Voltage | β | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | β | Industrial (-40 Β°C to +100 Β°C junction) |
| Moisture Sensitivity Level (MSL) | β | 3 (per Vyrian listing) |
| Peak Reflow Temperature | β | 220 Β°C (per Vyrian listing) |
| Configuration Method | β | JTAG / serial configuration EPROM |
| Supported I/O Standards | β | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | β | Obsolete - consult Altera / Intel FPGA archive for documentation |