EP2A40F1020C8N vs EP2A40F1020I9 Comparison
Detailed side-by-side comparison of EP2A40F1020C8N by Intel and EP2A40F1020I9 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A40F1020C8N | EP2A40F1020I9 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $2,105.00 |
| Product Type | Field-Programmable Gate Array (FPGA) | β |
| Device Family | APEX II | β |
| Logic Technology | CMOS | β |
| Logic Gates | 1.5 million | β |
| Logic Cells | 38,400 | 38,400 |
| Nominal Supply Voltage | 1.5 V | β |
| Supply Voltage Range | 1.425 V to 1.575 V | β |
| User I/Os | 735 | β |
| Package Terminal Count | 1,020 pins | β |
| Package Type | FC-FBGA, BGA-1020 | β |
| Package Body Size | 33 mm x 33 mm | β |
| Ball Pitch | 1 mm | β |
| Reported Operating Frequency | 376 MHz | β |
| Alternative Reported Frequency | 562 MHz | β |
| Reported Propagation Delay | 1.78 ns | β |
| Alternative Reported Propagation Delay | 1.55 ns | β |
| Fabrication Process | 0.15 Β΅m | β |
| Maximum Reported Metal Layers | 8 layers | β |
| Operating Temperature | 0 Β°C to 85 Β°C | [DATA_NEEDED: junction temperature range for I9 grade] |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Terminal Form | Ball | β |
| RoHS Status | unknown | [DATA_NEEDED: confirm RoHS compliance for FC-FBGA] |
| REACH Status | unknown | β |
| AEC-Q100 Qualification | unknown | β |
| Family | β | APEX II |
| Series | β | EP2A |
| System Gates | β | 1.5 M |
| Maximum Operating Frequency | β | 366 MHz |
| Process Technology | β | 0.15 Β΅m |
| Core Voltage | β | 1.5 V |
| Package | β | 1020-pin FC-FBGA |
| Pin Count | β | 1020 |
| Temperature Grade | β | Industrial (I9) |
| Logic Element Type | β | 4-input LUT |
| Embedded Memory | β | ESBs (dual-port RAM / ROM / FIFO) |
| Configuration Method | β | JTAG / passive serial / passive parallel |