EP2A40F672C6N vs EP2A40F672C7ES Comparison
Detailed side-by-side comparison of EP2A40F672C6N by Intel and EP2A40F672C7ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2A40F672C7ES
EP2A40F672C7ES - APEX II 1.5M Gates FPGA 672-FBGA | Intel / Altera
EP2A40F672C7ES ObsoleteSpecification Comparison
| Parameter | EP2A40F672C6N | EP2A40F672C7ES |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $165.00 | $124.75 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | 38400 |
| Maximum System Gates | 1,125,000 | β |
| Embedded RAM Bits | 442,368 | β |
| Embedded System Blocks (ESBs) | 160 | β |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | β |
| Core Voltage | 1.5 V | β |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | β |
| Package | 672-ball FineLine BGA | 672-pin FC-FBGA (FineLine BGA) |
| Operating Temperature | Commercial (0C to +85C) | 0 Β°C to +85 Β°C (commercial) |
| Speed Grade | C6 (per part number suffix) | 7 |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 Β΅m CMOS |
| PLL Count | [DATA_NEEDED: PLL count] | β |
| Typical Gates | β | 1.5 M |
| Maximum Logic Elements | β | 40960 |
| Maximum Macro Cells | β | 2560 |
| Maximum User I/O | β | 492 |
| Maximum Operating Frequency | β | 562 MHz |
| Core Voltage (VCCINT) | β | 1.5 V |
| I/O Voltage (VCCIO) | β | 3.3 V |
| Package Dimensions | β | 27 Γ 27 mm |
| Ball Pitch | β | 1.0 mm |
| Status Code | β | ES (Engineering Sample) |