EP2A40F672C6N vs EP2A40F672C9ES Comparison
Detailed side-by-side comparison of EP2A40F672C6N by Intel and EP2A40F672C9ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2A40F672C6N | EP2A40F672C9ES |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $165.00 | $195.00 |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | 38,400 |
| Maximum System Gates | 1,125,000 | β |
| Embedded RAM Bits | 442,368 | β |
| Embedded System Blocks (ESBs) | 160 | β |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | β |
| Core Voltage | 1.5 V | 1.5 V |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | β |
| Package | 672-ball FineLine BGA | 672-pin FC-FBGA |
| Operating Temperature | Commercial (0C to +85C) | β |
| Speed Grade | C6 (per part number suffix) | -9 |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | β |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | unknown |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 Β΅m CMOS |
| PLL Count | [DATA_NEEDED: PLL count] | β |
| System Gates | β | 1,500,000 |
| Maximum User I/O | β | 492 |
| Operating Frequency (max) | β | 366 MHz |
| Configuration Modes | β | PS, PPS, PPA, JTAG, FPP |
| Embedded Memory (ESB) | β | Yes (RAM/ROM/CAM) |
| I/O Standards | β | LVTTL, LVCMOS, PCI, SSTL, HSTL, GTL+ |
| Boundary Scan | β | IEEE 1149.1 (JTAG) |