EP2A70B652C7 vs EP20K600CB652I8 Comparison
Detailed side-by-side comparison of EP2A70B652C7 by Intel and EP20K600CB652I8 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP20K600CB652I8
EP20K600CB652I8 - APEX 20KC 600K Gates FPGA | Intel | 652-BGA
EP20K600CB652I8 ObsoleteSpecification Comparison
| Parameter | EP2A70B652C7 | EP20K600CB652I8 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.51 | $92.00 |
| Manufacturer | Intel (formerly Altera) | β |
| Series | APEX II | EP20K600 |
| Family | APEX II (Field-Programmable Gate Array) | APEX 20KC |
| Logic Elements (LEs) | 67200 | β |
| Typical Gates | 1140000 | β |
| Maximum User I/Os | 336 | β |
| Package Type | BGA-652 (FineLine BGA) | β |
| Package Size | 27 mm x 27 mm (approximate) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Grade | Commercial (C) | β |
| Speed Grade | 7 | β |
| Core Voltage | 1.8 V | β |
| I/O Bank Voltage (VCCIO) | 1.5V / 1.8V / 2.5V / 3.3V (bank-dependent) | β |
| Configuration Interface | JTAG, Passive Serial | β |
| Memory Type | Embedded SRAM blocks (ESBs) | β |
| PLL / Clock Management | Yes, dedicated PLL blocks | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| System Gates | β | 600,000 |
| Logic Elements / Cells | β | 24,320 |
| Maximum Operating Frequency | β | 301.21 MHz |
| Propagation Delay (tpd) | β | 1.78 ns (CMOS) |
| Process Technology | β | 0.15 Β΅m CMOS |
| Core Supply Voltage (VCCINT) | β | 1.8 V nominal (1.71 V to 1.89 V) |
| Operating Temperature | β | -40 Β°C to +85 Β°C (Industrial) |
| Package | β | 652-ball FineLine BGA (S-PBGA-B652) |
| Package Code | β | BGA, square |
| Ball Pitch | β | 1.27 mm |
| Package Body Size | β | 45 mm Γ 45 mm |
| User I/O Lines | β | 488 |
| Dedicated Clock Inputs | β | 4 |
| Programming Interface | β | IEEE 1149.1 JTAG (in-system) |