EP2AGX190FF35I3G vs EP2AGZ300FF35I3G Comparison
Detailed side-by-side comparison of EP2AGX190FF35I3G by Altera and EP2AGZ300FF35I3G by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EP2AGX190FF35I3G - Arria II GX FPGA 190K LE | Intel | Altera
EP2AGX190FF35I3G β Last Time Buy
Specification Comparison
| Parameter | EP2AGX190FF35I3G | EP2AGZ300FF35I3G |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,840.00 | $1,230.00 |
| Family | Arria II GX | Arria II GZ |
| Logic Elements (LE) | 181,165 | 300000 |
| Adaptive Logic Modules (ALM) | [DATA_NEEDED: ALM count] | β |
| User I/O Pins | 612 | β |
| Embedded Memory (bits) | 10,177,536 | β |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | β |
| Transceivers | 8 high-speed transceiver channels (multi-gigabit) | β |
| Embedded Multipliers | [DATA_NEEDED: 18x18 multiplier count] | β |
| PLLs | [DATA_NEEDED: PLL count] | [DATA_NEEDED: number of PLLs] |
| Core Voltage | 0.9 V | β |
| I/O Voltage Standards | 1.2 V to 3.3 V (LVTTL, LVCMOS, LVDS, HSTL, SSTL) | β |
| Process Node | 40 nm | 40 nm |
| Operating Temperature | -40 Β°C to +100 Β°C (industrial, suffix I) | -40C to +100 C (I3 industrial) |
| Speed Grade | 3 | β |
| Package | 1152-ball FC-FBGA (FF35), 35 mm body | 1152-ball FBGA (FF35) |
| Ball Pitch | [DATA_NEEDED: 1.0 mm (typical for FF35)] | β |
| Mounting Type | Surface Mount (flip-chip BGA) | Surface Mount |
| RoHS Status | Compliant (suffix G) | Compliant |
| Lead-Free | Yes | Yes |
| Programming Toolchain | Quartus II / Quartus Prime | β |
| Number of User I/O | β | 554 (maximum) |
| Number of Transceivers | β | 8 |
| Transceiver Data Rate | β | Up to 6.375 Gbps |
| Supply Voltage | β | [DATA_NEEDED: core and I/O supply voltage values] |
| Embedded Memory (Mbits) | β | 16.4 |
| DSP Blocks | β | [DATA_NEEDED: number of DSP blocks] |
| Memory Interfaces | β | DDR3, QDRII+, RLDRAM II |
| Configuration Method | β | Serial, Parallel, JTAG |
| MSL Level | β | 3 (168 hours) |