EP2AGX65DF29C6G vs EP2AGX65DF29C4G Comparison
Detailed side-by-side comparison of EP2AGX65DF29C6G by Intel and EP2AGX65DF29C4G by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2AGX65DF29C6G - Arria II GX FPGA 60K LE 780-FBGA | Altera / Intel
EP2AGX65DF29C6G β Active
Specification Comparison
| Parameter | EP2AGX65DF29C6G | EP2AGX65DF29C4G |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $245.30 | $219.00 |
| Family | Arria II GX | Arria II GX |
| Logic Elements | 60,214 | 60,214 |
| Embedded Memory Bits | 5,371,904 | β |
| Embedded Memory (M9K blocks) | [DATA_NEEDED: M9K block count] | β |
| Number of I/O | 364 | β |
| User I/O Banks | [DATA_NEEDED: user I/O bank count] | β |
| Core Voltage | 0.9 V | 0.9 V |
| Supply Voltage Range | [DATA_NEEDED: full supply range] | β |
| Number of Transceivers | 12 | 8 |
| Transceiver Data Rate (max) | 6 Gbps (C6 speed grade) | β |
| Number of PLLs | 12 | β |
| Number of DSP Blocks | [DATA_NEEDED: DSP block count] | β |
| Number of 18x18 Multipliers | 12 | β |
| Process Technology | 40 nm | β |
| Package | 780-pin FC-FBGA | 780-BBGA, FCBGA (29 mm) |
| Mounting Type | Surface Mount (Flip-Chip BGA) | Surface Mount |
| Operating Temperature Range | 0C to +85C (Commercial) | β |
| Speed Grade | C6 (Commercial, mid-tier) | -4 (mid-speed) |
| RoHS Status | Compliant | Compliant |
| Lead-Free | Yes | β |
| Adaptive Logic Modules (ALMs) | β | 30,107 |
| Embedded Memory | β | 5,371,904 bits |
| Number of LABs/CLBs | β | 2,530 |
| User I/O Count | β | 364 |
| Transceiver Data Rate | β | up to 3.75 Gbps (6.5536 Gbps with -4 grade using CPRI mode) |
| Operating Frequency | β | 500 MHz |
| Operating Temperature | β | 0C to +85C (commercial) |
| Process Node | β | 40 nm (Arria II generation) |
| Lead Free | β | Yes |
| MSL Level | β | 3 (per JEDEC J-STD-020) |