EP2AGZ300FF35C4N vs EP2AGZ300FF35C3G Comparison
Detailed side-by-side comparison of EP2AGZ300FF35C4N by Altera and EP2AGZ300FF35C3G by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2AGZ300FF35C4N | EP2AGZ300FF35C3G |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,350.00 | $1,395.00 |
| Series | Arria II GZ | Arria II GZ |
| Logic Elements | 298,000 | 300,000 |
| Logic Array Blocks (LABs) | 11,920 | β |
| Embedded Memory (bits) | 18,854,912 (~17.9 Mbit) | β |
| User I/O Count | 554 | β |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | β |
| Process Technology | 40 nm | 40 nm TSMC |
| Core Voltage | 0.9 V | β |
| Package Type | 1152-BBGA, FCBGA (flip-chip) | β |
| Terminal Form | Ball | β |
| Package Code (JEDEC) | HBGA | β |
| Operating Temperature Grade | Commercial (C4 = 0C to +85C) | β |
| Configuration Memory | SRAM-based (volatile, requires boot device) | β |
| Transceivers | Multi-gigabit transceivers integrated | 16 channels, up to 6.375 Gbps |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks] | 16-bit x 18-bit x 18-bit multipliers, integer/fractional modes |
| PLLs | [DATA_NEEDED: PLL count] | β |
| RoHS Status | Compliant (per Besenchips / DigiKey listing) | Compliant |
| Lead-Free Status | Lead free (per Besenchips listing) | β |
| Mounting Type | Surface Mount | β |
| Maximum Operating Frequency | 500 MHz | β |
| Adaptive Logic Modules (ALMs) | β | 119,088 |
| Embedded Memory | β | 17,133 Kbit |
| Hard PCIe Controllers | β | Up to 12 (Gen2 endpoint/root-port) |
| User I/Os | β | 1,288 |
| I/O Banks | β | 12 |
| Package | β | FCBGA-1152 (35 mm) |
| Package Family | β | BGA (Flip-Chip) |
| Temperature Grade | β | Commercial (0 C to 85 C junction) |
| Speed Grade | β | 3 (mid-performance) |
| Configuration Method | β | Quartus II/Prime, JTAG, Passive Serial, Fast Passive Parallel |
| Hard Memory Controller | β | DDR3 up to 800 MHz, DDR2, QDR II+ |