EP2S130F1020C3N vs EP2S130F1020C5ES Comparison
Detailed side-by-side comparison of EP2S130F1020C3N by Intel and EP2S130F1020C5ES by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2S130F1020C3N - Stratix II FPGA, 132K LE, 742 I/O, 1020-FBGA | Intel
EP2S130F1020C3N β Last Time Buy
Specification Comparison
| Parameter | EP2S130F1020C3N | EP2S130F1020C5ES |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,095.00 | $1,380.00 |
| Manufacturer | Intel (formerly Altera) | β |
| Series | Stratix II | β |
| Logic Elements | 132,540 LE | 132,540 |
| Number of I/O | 742 | β |
| Package Type | 1020-FBGA (33x33 mm) | β |
| Operating Temperature | 0C to +85C (commercial) | β |
| Process Technology | 90 nm CMOS | 90 nm |
| Core Voltage | 1.2 V | 1.2 V |
| Embedded Memory | [DATA_NEEDED: exact TriMatrix memory size in Mbits] | β |
| Embedded Multipliers | 504 (18x18) | β |
| PLL Count | 12 (4 enhanced + 8 fast) | β |
| Transceivers | [DATA_NEEDED: high-speed transceiver count for this speed grade] | β |
| Mounting Type | Surface Mount (BGA) | Surface Mount |
| Lead Free Status | Lead Free | β |
| RoHS Status | RoHS Compliant | Compliant (lead-free) |
| Family | β | Stratix II |
| Embedded Memory Bits | β | 6,747,840 |
| Maximum User I/Os | β | 742 |
| Maximum Internal Clock Frequency | β | 609.76 MHz |
| Speed Grade | β | -5 |
| Package | β | 1020-ball FC-FBGA (flip-chip BGA) |
| Operating Temperature (Junction) | β | 0C to 85C (commercial) |
| Logic Array Blocks (LABs) | β | 6,747 |
| Adaptive Logic Modules (ALMs) | β | 53,016 |
| Total RAM Blocks | β | [DATA_NEEDED: total RAM blocks] |
| Embedded DSP Blocks | β | [DATA_NEEDED: embedded DSP blocks count] |
| Embedded 18x18 Multipliers | β | [DATA_NEEDED: 18x18 multiplier count] |
| PLLs | β | [DATA_NEEDED: PLL count] |
| Configuration | β | SRAM-based, JTAG/AS/PS modes |