EP2S130F1020C3NRB vs EP2S130F1020C5N Comparison
Detailed side-by-side comparison of EP2S130F1020C3NRB by Intel and EP2S130F1020C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2S130F1020C3NRB
EP2S130F1020C3NRB - Stratix II FPGA, 132K LE, 742 I/O, 1020-BBGA
EP2S130F1020C3NRB β Last Time BuyIntel
EP2S130F1020C5N
EP2S130F1020C5N - Stratix II FPGA, 132K LEs, 1020-FBGA | Intel
EP2S130F1020C5N NrndSpecification Comparison
| Parameter | EP2S130F1020C3NRB | EP2S130F1020C5N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,245.00 | $1,320.00 |
| Manufacturer | Intel Corporation (formerly Altera) | β |
| Series | Stratix II | β |
| Device Type | FPGA (Field Programmable Gate Array) | β |
| Logic Elements (LEs) | 132,540 | β |
| Total Memory | 6,748 Kbits | β |
| LABs/CLBs | 6,627 | β |
| User I/O Count | 742 | β |
| Package | 1020-BBGA (33x33 mm, 1.0 mm pitch) | 1020-ball FC-FBGA (33x33 mm) |
| Operating Temperature | 0C to +85C (commercial, C3 speed grade) | Commercial (0C to +85C, C5 grade) |
| Process Node | 90 nm | β |
| Mounting Type | Surface Mount | Surface Mount |
| Lead Free / RoHS Status | Lead Free / RoHS Compliant | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Voltage - Supply (VCCINT) | [DATA_NEEDED: VCCINT nominal] | β |
| Voltage - I/O Banks | [DATA_NEEDED: VCCIO range] | β |
| Family | β | Stratix II |
| Logic Elements | β | 132,540 |
| Adaptive Logic Modules (ALMs) | β | 6627 LABs (per Jotrin listing) |
| Total Memory Bits | β | 6,747,840 bits |
| User I/Os | β | 734 |
| Process Technology | β | 90 nm |
| Core Supply Voltage (VCCINT) | β | 1.15 V to 1.25 V |
| Maximum Internal Frequency | β | 609.76 MHz |
| Temperature Grade | β | C5 (other - per Partstack) |
| RoHS Status | β | [DATA_NEEDED: rohs status] |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |
| PLLs | β | 4 (typical Stratix II feature) |
| Global Clock Networks | β | 16 (typical Stratix II feature) |
| Configuration Method | β | Serial/Parallel via Quartus II (typical Stratix II) |
| Country of Origin | β | Republic of Korea (per GlobalSpec) |
| ECCN | β | 3A001.a.7.a (per GlobalSpec) |
| Estimated EOL Date | β | 2023 (per GlobalSpec) |