EP2S180F1508C4TT vs EP2S180F1508C4 Comparison

Detailed side-by-side comparison of EP2S180F1508C4TT by Altera and EP2S180F1508C4 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EP2S180F1508C4 EP2S180F1508C4 - 179,400-Cell Stratix II FPGA | Intel

EP2S180F1508C4 - 179,400-Cell Stratix II FPGA | Intel

EP2S180F1508C4 βœ“ Active

Specification Comparison

Parameter EP2S180F1508C4TT EP2S180F1508C4
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $0.00
Product Type Field-Programmable Gate Array (FPGA) Field Programmable Gate Array (FPGA)
Device Family Stratix II β€”
Logic Elements approximately 180,000 β€”
User I/O 1,170 pins β€”
Logic Array Blocks 8,970 LABs β€”
Package 1,508-ball FBGA β€”
Mounting Type Surface Mount β€”
Temperature Grade -T β€”
Configuration Mechanism [DATA_NEEDED: configuration mechanism] β€”
Operating Voltage [DATA_NEEDED: operating voltage] β€”
Core Voltage [DATA_NEEDED: core voltage] β€”
I/O Voltage [DATA_NEEDED: I/O voltage] β€”
Operating Temperature [DATA_NEEDED: operating temperature] [DATA_NEEDED: operating temperature range]
Storage Temperature [DATA_NEEDED: storage temperature] β€”
Package Dimensions [DATA_NEEDED: package dimensions] β€”
Ball Pitch [DATA_NEEDED: ball pitch] β€”
Typical Power Dissipation [DATA_NEEDED: typical power dissipation] β€”
RoHS Status unknown [DATA_NEEDED: RoHS status]
REACH Status unknown β€”
AEC-Q100 Qualification unknown β€”
Lead-Free Status unknown β€”
Halogen-Free Status unknown β€”
Series β€” Stratix II
Logic Elements/Cells β€” 179,400 cells
Total RAM Bits β€” 9,383,040 bits
Number of I/O β€” 1,170 I/O
Supply Voltage β€” 1.15 V to 1.25 V
Process Technology β€” 90 nm
Operating Frequency β€” 711.24 MHz
Supplier Device Package β€” 1508-FBGA (40 mm x 40 mm)
Package / Case β€” 1508-BBGA, FCBGA
Terminal Count β€” 1,508 terminals
Terminal Form β€” Ball
Packaging β€” Tray
Time@Peak Reflow Temperature-Max β€” 30 s
Moisture Sensitivity Level β€” MSL 4 (72 hours)
Package Shape β€” Square
Configuration Technology β€” SRAM-based FPGA

Datasheets & Resources

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