EP2S30F672C5NRB vs EP2S30F672I4 Comparison

Detailed side-by-side comparison of EP2S30F672C5NRB by Intel and EP2S30F672I4 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP2S30F672C5NRB EP2S30F672I4
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $180.00 $695.00
Series Stratix II Stratix II
Manufacturer Intel (formerly Altera) Intel (formerly Altera)
Logic Elements / Cells 33,880 β€”
Number of LABs / CLBs 1,694 β€”
Total RAM Bits [DATA_NEEDED: total embedded memory bits] 1369728
Number of I/O 500 500
Voltage - Supply (Core) 1.15 V to 1.25 V β€”
Mounting Type Surface Mount Surface Mount
Package / Case 672-BBGA 672-BBGA, FCBGA (FBGA-672)
Supplier Device Package 672-FBGA (27 x 27 mm) β€”
Operating Temperature 0 C to 85 C (TJ) -40C to +100C (Industrial)
Packaging Tray (NRB suffix = RoHS, no NRB = legacy) β€”
Process Technology 90 nm CMOS, SRAM-based configuration 90 nm CMOS
Configuration Method SRAM, configured via JTAG, PS, or FPP β€”
RoHS Status Compliant (NRB suffix) [DATA_NEEDED: confirm RoHS compliance on part label]
Product Status Obsolete (last time buy / end of life) β€”
Logic Elements β€” 33880
Logic Array Blocks (LABs) β€” 1694
DSP Blocks β€” 12 (per datasheet, family range)
Number of PLLs β€” 6
Voltage - Supply β€” 1.2 V core, separate I/O bank VCCIO
Package Dimensions β€” 35 x 35 mm
Ball Pitch β€” 1.0 mm
Configuration β€” JTAG, serial, parallel (Stratix II scheme)
MSL Level β€” 3 (per JEDEC J-STD-020)

Datasheets & Resources

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