EP2S30F672C5NRB - Stratix II FPGA 33.8K LE 500 I/O 672-FBGA | Intel
MPN: EP2S30F672C5NRB ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $285 | $285.00 |
| 10 | $265 | $2,650.00 |
| 100 | $235 | $23,500.00 |
| 500 | $205 | $102,500.00 |
| 1,000 | $180 | $180,000.00 |
EP2S30F672C5NRB Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device containing an array of configurable logic blocks (CLBs), embedded memory, DSP blocks, and high-speed transceivers that can be re-programmed by the customer after manufacture. FPGAs sit between general-purpose microcontrollers and application-specific integrated circuits (ASICs) in the design flexibility vs. performance trade-off, making them ideal for prototyping, low-volume production, and designs requiring hardware-level parallelism. The Stratix II family was Intel/Altera's second-generation high-performance FPGA, succeeding the original Stratix and adding adaptive logic modules (ALMs).
Key features of the EP2S30F672C5NRB include 1,694 LABs/CLBs, 33,880 total logic elements, embedded memory, DSP blocks for high-throughput arithmetic, and high-speed I/O support. The 672-FBGA package exposes up to 500 user I/O, allowing integration with DDR/DDR2 memory, LVDS links, and parallel high-speed buses. The device operates from a 1.15 V to 1.25 V core supply and supports configuration via passive serial, fast passive parallel, or JTAG.
Architecturally, the Stratix II device family is built on a 90 nm SRAM process with embedded memory, TriMatrix memory blocks, and dedicated DSP blocks capable of 9-bit, 18-bit, and 36-bit arithmetic at hundreds of MHz. The ALM (Adaptive Logic Module) architecture combines features of LUT-based and product-term-based logic, giving 1.4x the typical logic capacity of competing architectures of the same size. High-speed I/O support includes LVDS, LVPECL, and DDR memory interfaces.
Typical applications include high-speed digital signal processing (DSP), telecommunications line cards, video processing pipelines, military/aerospace secure communications, and ASIC prototyping. The 500 I/O count makes it especially suitable for memory-intensive and bus-intensive designs that require many concurrent external connections.
When designing with this part, note that configuration data must be loaded from an external flash or download cable on every power-up, as the SRAM-based configuration is volatile. Use the Quartus II design software for synthesis, place-and-route, and timing closure. The 672-BGA package requires careful PCB layout with matched-length traces and proper thermal management.
This page synthesizes distributor pricing, parametric alternatives, and engineering guidance for the EP2S30F672C5NRB not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2S30F672C5NRB — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S30F672C5NRB (same form factor and footprint) — differing in Speed Grade, Package, Operating Temperature, Process Technology, Logic Array Blocks (LABs).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S30F672C5N
✅ Drop-In✓ In Stock
$450 / Unit
View Datasheet →EP2S30F672C5NGC
✅ Drop-In✓ In Stock
$171 / Unit
View Datasheet →EP2S30F672C5
✅ Drop-In✓ In Stock
$155 / Unit
View Datasheet →EP2S30F672C4N
✅ Drop-In✓ In Stock
$121 / Unit
View Datasheet →EP2S30F672C3N
✅ Drop-In✓ In Stock
$55 / Unit
View Datasheet →EP2S60F672C5N
✅ Drop-In✓ In Stock
$170 / Unit
View Datasheet →EP2S30F672C5NRB Maximum Ratings & Electrical Characteristics
| Series | Stratix II |
| Manufacturer | Intel (formerly Altera) |
| Logic Elements / Cells | 33,880 |
| Number of LABs / CLBs | 1,694 |
| Number of I/O | 500 |
| Voltage - Supply (Core) | 1.15 V to 1.25 V |
| Mounting Type | Surface Mount |
| Package / Case | 672-BBGA |
| Supplier Device Package | 672-FBGA (27 x 27 mm) |
| Operating Temperature | 0 C to 85 C (TJ) |
| Packaging | Tray (NRB suffix = RoHS, no NRB = legacy) |
| Process Technology | 90 nm CMOS, SRAM-based configuration |
| Configuration Method | SRAM, configured via JTAG, PS, or FPP |
| RoHS Status | Compliant (NRB suffix) |
| Product Status | Obsolete (last time buy / end of life) |
EP2S30F672C5NRB 672-fbga (27 x 27 mm) Pin Configuration Guide
Pin configuration for EP2S30F672C5NRB (672-fbga (27 x 27 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S30F672C5NRB.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S30F672C5NRB is suitable for 6 applications: High-Speed Digital Signal Processing (DSP), Telecommunications Line Card Processing, ASIC Prototyping and Emulation, Video Processing and Image Pipelines, Military and Aerospace Secure Communications, Industrial Control and High-Speed Test Equipment.
High-Speed Digital Signal Processing (DSP)
The EP2S30F672C5NRB fits high-speed DSP applications because its dedicated hardware DSP blocks deliver 9-bit, 18-bit, and 36-bit signed arithmetic at up to 370 MHz, far faster than soft multipliers in the LE fabric. The 500 user I/O pins enable parallel connection to multi-channel ADC/DAC front ends and high-speed DDR memory buses. With 33,880 logic elements, the device comfortably fits mid-sized FFT, FIR filter, and digital-down-conversion pipelines used in software-defined radio and radar processing. Engineers typically achieve 50-70% logic utilization while sustaining timing closure at the -5 speed grade, leaving margin for design iterations.
Recommended
Telecommunications Line Card Processing
The EP2S30F672C5NRB is well suited to telecom line-card applications because the 500 I/O count supports multi-port SERDES, TDM bus interfaces, and switching fabric connections simultaneously. The Stratix II device's embedded memory and DSP blocks can handle packet classification, queue management, and traffic shaping at wire speed. The 672-FBGA package exposes LVDS-capable I/O for chip-to-chip interconnect to PHY devices and network processors. The 90 nm process delivers sufficient performance for OC-48/STM-16 line-rate processing at 2.5 Gbps aggregate.
Recommended
ASIC Prototyping and Emulation
For ASIC prototyping, the EP2S30F672C5NRB offers 33,880 LEs and abundant I/O for verifying RTL designs before tape-out. Its abundant M4K/M-RAM memory blocks preserve ASIC memory instances 1:1, simplifying RTL-to-FPGA partitioning. Engineers can map large portions of an ASIC RTL block-by-block, with the 500 I/O enabling multi-FPGA partitioning across breadboards. The Stratix II ALM architecture closely matches ASIC standard-cell behavior, making timing correlation between prototype and final silicon more predictable than older LUT-only architectures.
Recommended
Video Processing and Image Pipelines
The EP2S30F672C5NRB is appropriate for video processing because its parallel fabric and DSP blocks support real-time HD video codecs, scaling, and color-space conversion. The 500 I/O can ingest parallel video buses (BT.1120, BT.656, RGB) from camera sensors or HDMI receivers and output to display controllers. The 672-BGA package provides ample I/O bandwidth for multi-channel SD/HD pipelines. Embedded TriMatrix memory blocks serve as line buffers and frame stores, avoiding the need for external SRAM in many designs.
Recommended
Military and Aerospace Secure Communications
Although the EP2S30F672C5NRB is a commercial-grade part (0 C to 85 C), it has historically been used in military and aerospace secure-comms applications for cost-sensitive non-flight subsystems. Its reconfigurable fabric supports rapid iteration of encryption and spread-spectrum algorithms, and the volatile SRAM configuration is straightforward to clear on power-down for anti-tamper requirements. The 500 I/O enable connection to multiple radio data links and crypto accelerators. Note that for flight hardware, designers should select the EP2S30F672I5N industrial variant and apply additional derating analysis.
Recommended
Industrial Control and High-Speed Test Equipment
The EP2S30F672C5NRB suits industrial test and measurement because its 500 I/O and DSP blocks can drive multi-channel ADC capture and DAC waveform generation with sub-microsecond deterministic latency. The parallel fabric implements protocol-aware state machines for standards like PCIe Gen1, RapidIO, or custom LVDS backplanes. The 672-BGA with proper thermal design delivers reliable 24/7 operation in production test racks. The 33,880 LEs provide enough headroom to integrate control-plane glue logic alongside high-speed datapath DSP without resorting to a companion CPLD.
Recommended
Recommended Products Summary
Engineering reference data for EP2S30F672C5NRB — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S30F672C5N | EP2S30F672C5NGC | EP2S30F672C4N | EP2S30F672C3N | EP2S60F672C5N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 672-FBGA (27x27 mm) | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same | 672-FBGA (27x27 mm) - same |
| Logic Elements | 33,880 | 33,880 | 33,880 | 33,880 | 33,880 | 60,440 |
| Speed Grade | -5 (C5) | -5 (C5) | -5 (C5) | -4 (C4) | -3 (C3) | -5 (C5) |
| Number of I/O | 500 | 500 | 500 | 500 | 500 | 500 |
| Core Voltage | 1.15 V to 1.25 V | 1.15 V to 1.25 V | 1.15 V to 1.25 V | 1.15 V to 1.25 V | 1.15 V to 1.25 V | 1.15 V to 1.25 V |
| Operating Temperature | 0 C to 85 C | 0 C to 85 C | 0 C to 85 C | 0 C to 85 C | 0 C to 85 C | 0 C to 85 C |
| RoHS / Lead-Free | Yes (NRB suffix) | No (N suffix = non-RoHS legacy) | Yes (NGC suffix = Pb-free ball) | No (N suffix = non-RoHS legacy) | No (N suffix = non-RoHS legacy) | No (N suffix = non-RoHS legacy) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- RoHS-compliant lead-free finish (NRB suffix) (vs EP2S30F672C5N)
- Same package and pinout as EP2S60 - capacity upgrade path (vs EP2S60F672C5N)
- Mid-density Stratix II with 500 I/O (vs EP2S15F672C5N)
- -5 speed grade (faster than -4, -1) (vs EP2S30F672C4N)
Design Notes
The EP2S30F672C5NRB requires multiple power rails: 1.2 V core (VCCINT), 1.2 V PLL analog (VCC_PLL), and I/O voltages (VCCIO) that depend on the bank configuration (1.5 V, 1.8 V, 2.5 V, 3.3 V). Power-on sequencing must satisfy the Stratix II datasheet requirements: VCCINT must rise monotonically before VCCIO, and all supplies must reach regulation within 100 ms. Use a power supervisor (e.g., TPS3890) to monitor rails and hold the nCONFIG pin low until all rails are stable. Decoupling: place 0.1 uF X7R ceramics at every VCCINT/VCCIO ball pair plus 4.7 uF bulk capacitors on each rail, located within 100 mil of the BGA.
Estimated: the 672-FBGA package has a typical theta-JA of approximately 12 C/W with a 4-layer JEDEC test board and 0 m/s airflow. At 50% toggle rate and 1.2 V core, the EP2S30F672C5NRB can dissipate 3-5 W depending on design utilization. For continuous full-load operation, provision a thermal pad on the PCB connected to an inner ground plane through a 4x4 thermal via array. Without adequate cooling, the junction temperature can exceed 100 C and trigger thermal throttling or long-term reliability degradation. A 100 LFM airflow drops theta-JA to approximately 8 C/W.
The 672-FBGA has a 1.0 mm ball pitch, requiring 0.5 mm drill microvias and 0.4 mm trace width on the BGA breakout layer. Use a via-in-pad design with filled and plated-over microvias to escape the inner rows of balls; the standard dog-bone fanout will not fit on a single layer for the inner rows. The Quartus II board design file (generated by the Pin Planner) provides the ball map and recommended escape routing. Match all high-speed LVDS pair traces within 10 mil length mismatch and route over a continuous ground reference plane for 90 ohm differential impedance.
The SRAM-based configuration is volatile: on every power-up the EP2S30F672C5NRB must be re-loaded from a configuration flash (EPCS16/EPCS64) or via JTAG. A common pitfall is failing to verify the configuration bitstream CRC: a corrupted bitstream can latch the device into a state that draws excessive current. Enable the CONF_DONE and nSTATUS pull-ups per datasheet and add a watchdog to reset the board if configuration takes longer than the expected 100 ms. Also note that JTAG chain order matters when multiple devices share the bus - include the FPGA's TDI/TDO in the boundary-scan chain with appropriate bypass.
Compliance Information
RoHS compliant per NRB suffix designation in MPN. AEC-Q100 not applicable (this is an FPGA, not an automotive-grade IC). Halogen-free status not specified in the Intel datasheet; assume 'unknown' rather than guessing. Conflict-minerals compliance per Intel's regulatory disclosure.
