EP2S60F1020 vs EP2S60F1020C4N Comparison
Detailed side-by-side comparison of EP2S60F1020 by Altera and EP2S60F1020C4N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2S60F1020 | EP2S60F1020C4N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,495.00 | $67.00 |
| Family | Stratix II | Stratix II (EP2S60) |
| Logic Elements (LE) | 60,440 | β |
| Adaptive Logic Modules (ALM) | 30,220 | β |
| Total Embedded Memory Bits | 2,544,192 bits | β |
| Embedded Memory Type | TriMatrix (M512 / M4K / M-RAM) | β |
| DSP Blocks | 36 (18x18 multipliers) | β |
| Maximum User I/O | 718 | β |
| Package | 1020-BBGA (flip-chip BGA) | 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA) |
| Process Technology | 90 nm | 90 nm CMOS |
| Supply Voltage (Core) | 1.2 V | β |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | Passive Serial, Fast Passive Parallel, JTAG |
| PLLs | 12 (4 enhanced + 8 fast) | β |
| Bitstream Encryption | 128-bit AES | β |
| Operating Temperature Grades | Commercial (C), Industrial (I) | β |
| RoHS Status | Compliant (lead-free variants available) | EU RoHS compliant with exemption (per Arrow listing) |
| Series | β | Stratix II |
| Logic Elements | β | 60,440 |
| Adaptive Logic Modules (ALMs) | β | 30,220 (approx.) |
| Logic Array Blocks (LABs) | β | 3,022 |
| Embedded Memory (bits) | β | 2,544,192 |
| Embedded Memory Blocks | β | M512/M4K/M-RAM TriMatrix memory |
| DSP Blocks (18-bit x 18-bit) | β | Up to 48 (24 per DSP block column pair typical) |
| User I/Os | β | 718 |
| Maximum Core Frequency | β | 711.24 MHz (per Arrow listing) |
| Core Voltage | β | 1.2 V |
| Mounting Type | β | Surface Mount (BGA) |
| Operating Temperature Grade | β | Commercial (C4 suffix indicates commercial, speed grade 4) |
| PLLs / Clock Networks | β | Yes - on-chip PLLs and global clock networks |