EP2S60F672C3N vs EP2S60F672C4N Comparison

Detailed side-by-side comparison of EP2S60F672C3N by Intel and EP2S60F672C4N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP2S60F672C3N EP2S60F672C4N
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $1,175.00 $325.00
Family Stratix II Stratix II
Logic Elements (LE) 60,440 60,440
Logic Array Blocks (LABs) 3,022 β€”
Adaptive Logic Modules (ALMs) 24,176 β€”
Total Embedded Memory 2,544,192 bits (2.5 Mbits) β€”
User I/O Pins 492 β€”
User I/O Banks 8 β€”
Process Technology 90 nm CMOS 90 nm
Core Supply Voltage (VCCINT) 1.2 V β€”
I/O Supply Voltage (VCCIO) 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) β€”
Pre-Driver Supply (VCCPD) 3.3 V β€”
Maximum Internal Clock Frequency 816.99 MHz β€”
PLLs 4 β€”
Global Clock Networks 16 β€”
Package 672-pin FC-FBGA 672-pin FC-FBGA
Mounting Type Surface Mount Surface Mount
Operating Temperature 0C to +85C (commercial grade) 0C to +85C (commercial)
Speed Grade C3 (slower speed grade) C4 (commercial)
RoHS Status unknown β€”
Lead-Free unknown β€”
Adaptive Logic Modules (ALM) β€” 24,176
Embedded Memory (bits) β€” 2,544,192
Embedded Multiplier Blocks β€” [DATA_NEEDED: 9x9 multiplier count]
DSP Blocks β€” [DATA_NEEDED: DSP block count]
Maximum User I/O β€” 492
Core Voltage β€” 1.2 V
Maximum Fabric Clock β€” 711.24 MHz
Package Type β€” FineLine Ball-Grid Array
Configuration Method β€” JTAG, Fast Passive Parallel, Active Serial
MSL Level β€” 3
Lead-Free / RoHS β€” Yes (lead-free finish)

Datasheets & Resources

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