EP2S60F672C5 vs EP2S15F672C4 Comparison
Detailed side-by-side comparison of EP2S60F672C5 by Intel and EP2S15F672C4 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP2S60F672C5 | EP2S15F672C4 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $410.85 | $235.00 |
| Family | Stratix II | Stratix II |
| Device Family | Stratix II FPGA | β |
| Logic Elements | 60,440 | 15,600 |
| Configurable Logic Blocks (CLBs) | 24,176 | β |
| Total RAM Bits | 2,544,192 bits | β |
| Maximum User I/Os | 492 | 366 |
| Operating Frequency | Up to 609.76 MHz | β |
| Core Voltage | 1.2 V | β |
| Process Technology | 90 nm CMOS | β |
| Package | 672-ball FC-FBGA (35 Γ 35 mm, 1 mm pitch) | 672-ball FineLine BGA (FBGA) |
| Mounting Type | Surface Mount | β |
| Operating Temperature Grade | Commercial (C5 suffix) | β |
| Operating Temperature Range | 0Β°C to +85Β°C | β |
| Number of PLLs | 4 | β |
| DSP Blocks | 12 (dedicated 18 Γ 18 multipliers) | 156 (approximate, per Stratix II family) |
| I/O Standards | LVDS, LVTTL, SSTL, HSTL, PCI-X | β |
| Configuration Scheme | Fast Passive Parallel, JTAG, Active Serial | β |
| RoHS Status | Non-RoHS (legacy product, pre-RoHS production runs) | [DATA_NEEDED: RoHS compliance per Altera product page] |
| Embedded Memory Bits | β | 419,328 bits |
| Process Node | β | 90 nm |
| PLLs | β | 6 |
| Operating Temperature | β | Commercial (0C to +85C, 'C' suffix) |
| Speed Grade | β | 4 |
| Configuration Method | β | Serial / Parallel (passive serial, fast passive parallel, JTAG) |
| I/O Standards Supported | β | LVTTL, LVCMOS, LVDS, SSTL, HSTL (per Stratix II family) |
| Lead-Free | β | [DATA_NEEDED: lead-free finish status] |
| MSL Level | β | [DATA_NEEDED: MSL moisture sensitivity level] |