EP2S60F672C5 - Stratix II FPGA 60K LEs 672-FBGA | Intel
MPN: EP2S60F672C5 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $547.8 | $547.80 |
| 5 | $520.41 | $2,602.05 |
| 10 | $493.02 | $4,930.20 |
| 25 | $465.63 | $11,640.75 |
| 100 | $410.85 | $41,085.00 |
EP2S60F672C5 Overview
A Field-Programmable Gate Array (FPGA) is a type of integrated circuit containing an array of configurable logic blocks (CLBs), programmable interconnect, and dedicated hardware blocks such as memory, DSP slices, and high-speed transceivers. FPGAs sit in the broader semiconductor taxonomy as programmable logic devices, distinct from fixed-function ASICs because their logic function is defined post-manufacture via a configuration bitstream. Stratix II devices are positioned at the high-performance end of the FPGA market and were widely adopted for ASIC prototyping and high-throughput DSP.
Key features of the EP2S60F672C5 include 24,176 CLBs (configurable logic blocks) per the FindIC specification listing, 12 dedicated DSP blocks for hardware-accelerated multiplication, up to 36 embedded RAM blocks (M4K/M-RAM), and 4 phase-locked loops (PLLs) for clock management. The device also incorporates 8 high-speed transceiver channels on selected die revisions and supports LVDS, LVTTL, SSTL, and HSTL I/O standards. The 672-pin FC-FBGA package measures 35 mm × 35 mm with 1 mm ball pitch, enabling high-density board integration while maintaining signal integrity.
Architecturally, the Stratix II family introduced the adaptive logic module (ALM) concept, replacing traditional 4-input LUTs with 8-input fracturable LUTs that improve logic packing efficiency by 25–40%. Combined with the dedicated DSP blocks and TriMatrix memory, the EP2S60F672C5 supports sustained DSP throughput exceeding 300 GMACs at the rated core frequency, making it suitable for video processing, baseband modulation, and high-channel-count instrumentation.
Typical applications for the EP2S60F672C5 include ASIC and SoC prototyping, software-defined radio (SDR) baseband processing, military/aerospace signal processing, high-end medical imaging front-ends, and high-throughput wireline communication. Engineers continue to deploy this part in long-lifecycle industrial and defense platforms where the mature Quartus II toolchain and proven silicon reliability outweigh the benefits of newer families.
A key design consideration is that the EP2S60F672C5 operates in the commercial temperature range (0°C to +85°C) - the I4 and I5 suffixes denote industrial and extended temperature grades respectively. Designers should also note that Stratix II devices require a 1.2 V core supply with separate VCCIO bank voltages, and the configuration scheme (typically fast passive parallel or JTAG) must be selected during PCB layout.
This page synthesizes distributor pricing, parametric specifications, drop-in alternatives, and practical design considerations not found in the manufacturer datasheet alone.
Drop-in alternatives for EP2S60F672C5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S60F672C5 (same form factor and footprint) — differing in Speed Grade, Package, Operating Temperature, RoHS Status, DSP Blocks.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP2S60F672C5N
✅ Drop-In✓ In Stock
$170 / Unit
View Datasheet →EP2S60F672C4
✅ Drop-In✓ In Stock
$1080 / Unit
View Datasheet →EP2S60F672C3
✅ Drop-In✓ In Stock
$1033.14 / Unit
View Datasheet →EP2S60F672C4N
✅ Drop-In✓ In Stock
$325 / Unit
View Datasheet →EP2S60F672I4
✅ Drop-In✓ In Stock
$1050 / Unit
View Datasheet →EP2S60F672C5 Maximum Ratings & Electrical Characteristics
| Family | Stratix II |
| Device Family | Stratix II FPGA |
| Logic Elements | 60,440 |
| Configurable Logic Blocks (CLBs) | 24,176 |
| Total RAM Bits | 2,544,192 bits |
| Maximum User I/Os | 492 |
| Operating Frequency | Up to 609.76 MHz |
| Core Voltage | 1.2 V |
| Process Technology | 90 nm CMOS |
| Package | 672-ball FC-FBGA (35 × 35 mm, 1 mm pitch) |
| Mounting Type | Surface Mount |
| Operating Temperature Grade | Commercial (C5 suffix) |
| Operating Temperature Range | 0°C to +85°C |
| Number of PLLs | 4 |
| DSP Blocks | 12 (dedicated 18 × 18 multipliers) |
| I/O Standards | LVDS, LVTTL, SSTL, HSTL, PCI-X |
| Configuration Scheme | Fast Passive Parallel, JTAG, Active Serial |
| RoHS Status | Non-RoHS (legacy product, pre-RoHS production runs) |
EP2S60F672C5 Pin Configuration
| Pin 1 | I/O Bank 1 — User I/O pin (function varies by pin assignment) |
| Pin 168 | GND — Ground reference |
| Pin 336 | VCCINT — Core voltage 1.2 V supply |
| Pin 504 | VCCIO — I/O bank voltage reference |
| Pin 672 | I/O Bank 8 — User I/O pin (function varies by pin assignment) |
Typical Applications
EP2S60F672C5 is suitable for 6 applications: ASIC and SoC Prototyping, Software-Defined Radio Baseband, Video Processing and Image Pipelines, Telecom Wireline Infrastructure, Military and Aerospace Signal Processing, High-End Test and Measurement Instrumentation.
ASIC and SoC Prototyping
The EP2S60F672C5's 60,440 logic elements and 2,544,192 bits of embedded RAM provide sufficient capacity to prototype mid-complexity ASIC and SoC designs before tape-out. Engineers map RTL designs into the Stratix II ALM architecture and verify functionality at hardware speeds, eliminating costly respins. The 492 user I/Os accommodate realistic stimulus and observation pads for full-system bring-up. Compared to simulation, hardware prototyping runs orders of magnitude faster and catches timing bugs that RTL simulation misses.
Recommended
Software-Defined Radio Baseband
The EP2S60F672C5's 12 dedicated DSP blocks deliver hardware-accelerated multiplication and accumulation, enabling real-time baseband processing for software-defined radio (SDR) platforms. Combined with the 609.76 MHz internal clock rate and 24,176 CLBs, the device can implement FFTs, channelizers, and digital downconverters at sample rates exceeding 100 MSPS. The LVDS I/O support simplifies interface to high-speed ADCs and DACs common in SDR front-ends.
Recommended
Video Processing and Image Pipelines
The EP2S60F672C5 is well-suited to high-resolution video processing, including scaling, deinterlacing, color space conversion, and real-time video analytics. The 2,544,192 bits of embedded RAM support line buffers and frame buffers for 1080p and beyond, while the 492 I/Os accommodate parallel video buses such as BT.1120 and CameraLink interfaces. The dedicated DSP blocks enable real-time pixel processing without CPU offload overhead.
Recommended
Telecom Wireline Infrastructure
The EP2S60F672C5's high logic density and dedicated DSP resources support line-card processing in central-office and aggregation telecom platforms. The Stratix II device handles channelized T1/E1 processing, framer/mapper functions, and packet classification at line rate, while the embedded M-RAM blocks provide deep packet buffering. The commercial temperature range and mature 90 nm silicon make it reliable for 24/7 telecom deployments.
Recommended
Military and Aerospace Signal Processing
Defense and aerospace platforms continue to use the EP2S60F672C5 in long-lifecycle radar, electronic-warfare, and secure-communications systems because of its proven reliability and available industrial temperature variants (I4 suffix). The 60,440 logic elements enable real-time beamforming, pulse compression, and adaptive filtering in radar front-ends. Designers should source parts through AS6081-certified brokers to mitigate counterfeit risk on legacy silicon.
Recommended
High-End Test and Measurement Instrumentation
The EP2S60F672C5 supports digital oscilloscope, logic analyzer, and protocol analyzer front-end processing, where its 492 user I/Os and high-speed LVDS capability are essential for sampling at multi-GSPS rates. Real-time triggering, pattern matching, and protocol decoding all leverage the device's 24,176 CLBs and dedicated DSP blocks. The mature Quartus II toolchain ensures reproducible design implementation across multiple product revisions.
Recommended
Recommended Products Summary
Engineering reference data for EP2S60F672C5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S60F672C5N | EP2S60F672C4 | EP2S60F672C3 | EP2S60F672C4N | EP2S60F672I4 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 672-ball FC-FBGA | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same | 672-ball FC-FBGA - same |
| Logic Elements | 60,440 | 60,440 | 60,440 | 60,440 | 60,440 | 60,440 |
| User I/Os | 492 | 492 | 492 | 492 | 492 | 492 |
| Speed Grade | C5 (fastest commercial) | C5 | C4 | C3 (slowest) | C4 | I4 |
| Temperature Grade | Commercial (0°C to +85°C) | Commercial | Commercial | Commercial | Commercial | Industrial (-40°C to +100°C) |
| Lead-Free / RoHS | Non-RoHS | RoHS-compliant (N suffix) | Non-RoHS | Non-RoHS | RoHS-compliant (N suffix) | Non-RoHS |
| Process / Core Voltage | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V | 90 nm / 1.2 V |
Key Differentiators
- Highest speed grade in Stratix II family (vs EP2S60F672C4)
- Lead-free RoHS compliance option (vs EP2S60F672C5)
- Industrial temperature grade option (vs EP2S60F672C5)
Design Notes
The Stratix II EP2S60F672C5 requires a regulated 1.2 V core supply (VCCINT) with ±5% tolerance and separate VCCIO bank voltages per I/O standard used. Power sequencing requirements: VCCINT must ramp before or simultaneously with VCCIO to avoid latch-up; all VCC rails must reach steady state within 100 ms. Estimated: at maximum toggle activity, the EP2S60 consumes 8-12 W from VCCINT; designers should budget at least 15 W for core supply headroom and provide adequate bulk decoupling.
The 672-ball FC-FBGA package uses 1 mm ball pitch and requires microvia (HDI) PCB technology for breakout routing. At least 6 PCB layers are recommended: a dedicated ground plane beneath the BGA, two signal layers for breakouts, two power planes for VCCINT and VCCIO, and a top layer for component placement. Use a 4-layer stack-up at minimum - this requires blind/buried vias and increases PCB cost. Maintain continuous ground reference beneath all high-speed LVDS traces.
Do not confuse speed grade suffix letters: C5 is the fastest commercial bin, C4 and C3 are progressively slower, and I4/5 are industrial temperature bins. Using C3 in a design that requires C5 timing may fail timing closure. Configuration mode selection (FPP, AS, JTAG) is committed in the Quartus II project - changing it post-compile requires recompilation. For obsolete parts, always verify lot date codes and source from franchised distributors to avoid counterfeit risk.
Compliance Information
Legacy Stratix II pre-dates mandatory RoHS. EP2S60F672C5N variant is lead-free RoHS-compliant. AEC-Q100 not applicable for FPGA logic devices.
