EP2S90F1020I4GA vs EP2S90F1020C3N Comparison
Detailed side-by-side comparison of EP2S90F1020I4GA by Intel and EP2S90F1020C3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2S90F1020I4GA - 90K LEs Stratix II FPGA, 758 I/O FBGA-1020 | Intel
EP2S90F1020I4GA β Last Time BuyAltera
EP2S90F1020C3N - 90nm Stratix II FPGA 90,960 LEs FC-FBGA-1020 | Altera
EP2S90F1020C3N β Last Time BuySpecification Comparison
| Parameter | EP2S90F1020I4GA | EP2S90F1020C3N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $220.00 | $1,995.00 |
| Family | Stratix II | Stratix II (EP2S90) |
| Logic Elements (LEs) | 90,960 | β |
| Embedded Memory | 4,520,488 bits (approximately 4.4 Mbit) | β |
| Embedded 18x18 Multipliers | 192 | β |
| Maximum User I/O | 758 | β |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Package | 1020-ball FC-FBGA | β |
| Operating Temperature | -40C to +100C (industrial) | 0C to +85C (commercial grade) |
| Speed Grade | I4 (mid-performance, industrial) | C3 (commercial, slowest) |
| Supply Voltage - Core (VCCINT) | 1.2 V nominal | β |
| Configuration Modes | Passive Serial, Fast Passive Parallel, JTAG | β |
| PLLs | 4 enhanced PLLs | β |
| External Memory Support | DDR, DDR2, QDRII, SDR | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant | Compliant |
| Program Memory Type | SRAM (volatile, requires configuration device) | β |
| Series | β | Stratix II |
| Logic Elements | β | 90,960 |
| LABs (Logic Array Blocks) | β | 4,548 |
| Total RAM Bits | β | 4,520,488 |
| User I/O Count | β | 758 |
| Supply Voltage - Core | β | 1.15 V to 1.25 V (1.2 V nominal) |
| Package / Case | β | 1020-BBGA, FC-FBGA |
| Supplier Device Package | β | 1020-FBGA (33 x 33 mm) |
| DSP Block Count | β | [DATA_NEEDED: 18x18 multiplier count] |
| Embedded Transceivers | β | [DATA_NEEDED: number of high-speed transceivers] |
| Maximum User I/O Frequency | β | [DATA_NEEDED: LVDS / DDR max rate] |
| MSL Level | β | 3 (per JEDEC J-STD-020) |
| Programming Tool | β | Altera Quartus II |