EP2S90F1020C3N - 90nm Stratix II FPGA 90,960 LEs FC-FBGA-1020 | Altera
MPN: EP2S90F1020C3N β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $2850 | $2,850.00 |
| 10 | $2695 | $26,950.00 |
| 100 | $2450 | $245,000.00 |
| 500 | $2200 | $1,100,000.00 |
| 1,000 | $1995 | $1,995,000.00 |
EP2S90F1020C3N Overview
An FPGA (Field-Programmable Gate Array) is a semiconductor device built from an array of configurable logic blocks, embedded memory, DSP slices, and programmable interconnect that the designer tailors after manufacture using a hardware-description language (HDL) bitstream. FPGAs sit between fixed-function ASICs and software-programmable processors, offering hardware-level parallelism with software-level flexibility. The Stratix II family in particular targets high-performance applications such as DSP, video processing, and high-speed serial interfacing where deterministic latency and parallel datapaths are required.
The EP2S90F1020C3N delivers up to 90,960 equivalent logic elements (LEs), 4,520,488 bits of TriMatrix embedded memory, and embedded DSP blocks for 18x18 multipliers. It supports external memory interfaces including DDR2 SDRAM, QDRII SRAM, and RLDRAM II via dedicated PHY, and includes high-speed LVDS and differential signaling capable of several hundred MHz. The C3 speed grade denotes a commercial-temperature part at the slowest of three Stratix II speed bins, favoring design closure and timing margin over maximum Fmax.
The Stratix II architecture uses an adaptive logic module (ALM) that combines fracturable 6-input LUT capability with dedicated register and carry resources, giving the part a logic-efficiency advantage over older 4-LUT architectures. Combined with a hierarchical interconnect structure and on-chip PLL / clock networks, the EP2S90F1020C3N typically achieves core performance in the 200-300 MHz range for general logic and significantly higher for dedicated DSP and memory paths.
Typical applications for EP2S90F1020C3N include high-speed digital signal processing, baseband and protocol processing in telecom, video and image processing pipelines, ASIC prototyping, high-speed data acquisition, and custom compute accelerators. Its large on-chip memory and high I/O count suit designs that need to keep data on-die to avoid off-chip memory bottlenecks.
When designing with this part, pay careful attention to the FC-FBGA-1020 package - it requires multilayer PCB with controlled-impedance routing, microvia or via-in-pad technology, and strict power-integrity decoupling. Designers typically use Altera (now Intel) Quartus II design software for synthesis, place-and-route, and timing analysis. The C3 speed grade is the slowest tier, so engineers targeting the highest Fmax should evaluate the C4 or C5 speed grades or step up to Stratix II GX variants for integrated transceivers.
This page synthesizes distributor pricing, drop-in Stratix II alternatives, and practical design guidance that consolidates information not found in a single manufacturer datasheet.
Drop-in alternatives for EP2S90F1020C3N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP2S90F1020C3N (same form factor and footprint) β differing in Package, Speed Grade, Operating Temperature, Embedded DSP Blocks, Embedded Multipliers (18x18).
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP2S90F1020C3
β Drop-Inβ In Stock
$640 / Unit
View Datasheet βEP2S90F1020C4N
β Drop-Inβ In Stock
$1320 / Unit
View Datasheet βEP2S90F1020I4N
β Drop-Inβ In Stock
$1995 / Unit
View Datasheet βEP2S90F1020C5N
β Drop-Inβ In Stock
$1240 / Unit
View Datasheet βEP2S130F1020C3N
β Drop-Inβ In Stock
$1095 / Unit
View Datasheet βEP2S60F1020C3N
β Drop-Inβ In Stock
$1095 / Unit
View Datasheet βEP2S90F1020C3N Maximum Ratings & Electrical Characteristics
| Series | Stratix II |
| Family | Stratix II (EP2S90) |
| Logic Elements | 90,960 |
| LABs (Logic Array Blocks) | 4,548 |
| Total RAM Bits | 4,520,488 |
| User I/O Count | 758 |
| Supply Voltage - Core | 1.15 V to 1.25 V (1.2 V nominal) |
| Process Technology | 90 nm CMOS |
| Operating Temperature | 0C to +85C (commercial grade) |
| Speed Grade | C3 (commercial, slowest) |
| Package / Case | 1020-BBGA, FC-FBGA |
| Supplier Device Package | 1020-FBGA (33 x 33 mm) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
| MSL Level | 3 (per JEDEC J-STD-020) |
| Programming Tool | Altera Quartus II |
EP2S90F1020C3N 1020-fbga (33 x 33 mm) Pin Configuration Guide
Pin configuration for EP2S90F1020C3N (1020-fbga (33 x 33 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP2S90F1020C3N.
Refer to the datasheet for full pin configuration.
Typical Applications
EP2S90F1020C3N is suitable for 6 applications: High-Speed Digital Signal Processing, Telecom Baseband and Protocol Processing, Video and Image Processing Pipelines, ASIC Prototyping and Emulation, High-Speed Data Acquisition, Industrial Control and Custom Compute Accelerators.
High-Speed Digital Signal Processing
The EP2S90F1020C3N's 90,960 logic elements combined with embedded 18x18 multipliers make it well-suited for high-throughput DSP pipelines such as FFT, FIR filtering, and baseband demodulation. The 4.5 Mbit TriMatrix memory delivers concurrent read/write bandwidth that keeps multiple taps of an FIR or butterfly stages fed without external memory contention. A typical design places 256 to 512 multipliers in parallel at 200+ MHz, achieving 50-100 GMACS performance. This density lets designers implement multi-channel radar, software-defined radio, or multi-antenna processing on a single chip. The C3 commercial speed grade biases for timing-margin favor over absolute Fmax, helping DSP pipelines meet timing closure without aggressive pipeline insertion.
Recommended
Telecom Baseband and Protocol Processing
Telecom baseband designs benefit from the EP2S90F1020C3N's 758 user I/O and dedicated external memory interface, which together support multi-standard framer/mapper and packet-processing pipelines. The device's 1.2 V core and 90 nm process deliver low dynamic power relative to older 130 nm Stratix devices, while the abundant on-chip memory enables deep packet inspection without DDR round-trips. Engineers typically instantiate a 10 Gbps-class MAC plus classifier using 60-80% of available LEs. The 1020-FBGA package exposes enough LVDS pairs for SFI / XAUI-style parallel interfaces, and the TriMatrix memory can be partitioned as look-up tables for FEC or rate-matching buffers.
Recommended
Video and Image Processing Pipelines
The EP2S90F1020C3N is a common choice for real-time video processing because it can ingest multi-channel SDI or DisplayPort streams, perform color-space conversion, scaling, and overlay blending, and output HDMI or SDI simultaneously. The 758 user I/Os accept parallel RGB/YUV buses at 150-200 MHz, and the embedded multipliers accelerate 2D convolution, scaling filters, and motion compensation. With 4.5 Mbit of TriMatrix memory, designers can line-buffer two HD frames at 10 bits per pixel in on-die RAM. The C3 speed grade supports typical 1080p60 throughput when the design is properly pipelined, and the package's thermal envelope handles the 5-8 W typical video-pipeline power budget without active cooling.
Recommended
ASIC Prototyping and Emulation
The EP2S90F1020C3N has long been a workhorse for ASIC and ASSP prototyping because its 90,960 LEs can absorb 1-2 million gates of synthesized logic plus on-chip memory models. Engineers use the abundant I/O and LVDS bandwidth to map multi-clock-domain ASIC blocks onto the FPGA's clock network, while the 4.5 Mbit TriMatrix serves as a fast scratchpad for cache and FIFO models. With Quartus II's multi-FPGA partition flow, multiple EP2S90 boards can be tiled to prototype larger ASICs. The 1020-FBGA package exposes enough user I/O (758) to bring out wide on-chip buses, JTAG chains, and external trace buffers for debug.
Recommended
High-Speed Data Acquisition
Data-acquisition systems digitize wide analog front ends into the EP2S90F1020C3N's LVDS or parallel CMOS I/O, where the FPGA performs real-time decimation, windowing, and trigger logic. The 4.5 Mbit TriMatrix can be partitioned as a deep circular sample buffer, supporting sustained 16-channel 250 MSPS capture without external SRAM for short bursts. Designers can also leverage dedicated PLL and clock networks to align multiple analog-to-digital converters. The C3 speed grade easily handles 200 MHz datapath clocks, and the 1020-FBGA package's signal integrity supports several hundred MHz of source-synchronous LVDS without de-rating.
Recommended
Industrial Control and Custom Compute Accelerators
In industrial automation, the EP2S90F1020C3N serves as a deterministic, low-latency controller for motor drives, PLC backplanes, and machine-vision sorters. Its 758 user I/O accommodate encoder feedback, sigma-delta front ends, and parallel digital buses, while the abundant logic elements and DSP blocks accelerate custom control loops. For compute-acceleration cards, designers use the device as a pre-DDR pre-processor that streams filtered data to a host CPU or GPU. The commercial temperature range suits factory-floor enclosures; for harsher environments, the industrial EP2S90F1020I4N variant in the same package extends operation to -40C to +100C with identical pinout and bitstream compatibility.
Recommended
Recommended Products Summary
Engineering reference data for EP2S90F1020C3N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP2S90F1020C3 | EP2S90F1020C4N | EP2S90F1020I4N | EP2S130F1020C3N | EP2S60F1020C3N |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 1020-FBGA (33x33 mm) | 1020-FBGA (33x33) - same | 1020-FBGA (33x33) - same | 1020-FBGA (33x33) - same | 1020-FBGA (33x33) - same | 1020-FBGA (33x33) - same |
| Logic Elements | 90,960 LEs | 90,960 LEs | 90,960 LEs | 90,960 LEs | 132,540 LEs | 60,440 LEs |
| Embedded RAM | 4,520,488 bits | 4,520,488 bits | 4,520,488 bits | 4,520,488 bits | 6,747,840 bits | 2,544,192 bits |
| User I/O Count | 758 | 758 | 758 | 758 | 742 | 718 |
| Speed Grade | C3 (slowest) | C3 | C4 (mid, +15-20% Fmax) | I4 (industrial, mid) | C3 | C3 |
| Operating Temperature | 0C to +85C (commercial) | 0C to +85C | 0C to +85C | -40C to +100C (industrial) | 0C to +85C | 0C to +85C |
| Core Voltage | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V | 1.2 V |
Key Differentiators
- Mid-density sweet spot in Stratix II family (vs EP2S60F1020C3N)
- Lower-cost pin-compatible alternative to EP2S130F1020C3N (vs EP2S130F1020C3N)
- C3 speed grade provides highest timing margin (vs EP2S90F1020C4N)
Design Notes
The 1020-FBGA (33 x 33 mm) package with 1.0 mm ball pitch requires a multilayer PCB (typically 8-12 layers) with microvia or via-in-pad technology. Assign at least one solid ground plane directly beneath the BGA and a second dedicated power island for VCCINT (1.2 V). Use the Altera Stratix II board design guidelines for via escape, decoupling capacitor placement, and trace-impedance targets. Signal-integrity simulations are recommended for any LVDS or DDR2 interface exceeding 200 MHz.
Estimated: at 200 MHz core clock and 70% utilization, EP2S90F1020C3N draws approximately 8-12 W from VCCINT and another 2-4 W from VCCIO banks, totaling 10-16 W system power. Use a multi-rail sequencer (such as a Linear Technology / Analog Devices LTC3714 or similar) to enforce VCCINT-to-VCCIO power-up sequencing within the limits specified in the Stratix II Handbook. Decouple VCCINT with at least 20 low-ESR ceramic capacitors (10 uF + 0.1 uF) placed as close to the balls as routing allows.
The 33 x 33 mm FC-FBGA package has a typical theta_JA around 12-15 C/W with proper PCB layout (including thermal vias to inner ground planes). Estimated: at 12 W total power, junction-to-ambient temperature rise is approximately 144-180 C above ambient, which exceeds commercial limits. For designs drawing more than 5 W, add a heatsink or forced-air cooling, or step down to a smaller Stratix II device with lower density. Always read the actual junction temperature via the on-chip temperature-sensing diode before finalizing cooling strategy.
Do not confuse the C3 commercial speed grade with C3 silicon revision - the digit is a speed bin, not a die stepping. Also, EP2S90F1020C3N is on Intel's last-time-buy list; do not start new design-ins without planning a forward migration to Cyclone IV/V, MAX 10, or Stratix 10. Quartus Prime does not support the legacy Stratix II family; retain a Quartus II 13.0 SP1 installation. When migrating to EP2S130F1020C3N for higher density, the pinout is not identical - 16 pins are no-connects on the EP2S90 that become user I/O on EP2S130, and vice versa.
Compliance Information
RoHS compliance confirmed via Altera/Intel product page. AEC-Q100 not applicable (industrial/commercial FPGAs). Halogen-free status not stated in distributor data; refer to Intel material declaration for confirmation. Conflict-minerals compliance per Intel published CMRT.
