EP2SGX30DF780C4 vs EP2SGX30DF780C4N Comparison
Detailed side-by-side comparison of EP2SGX30DF780C4 by Intel and EP2SGX30DF780C4N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP2SGX30DF780C4
EP2SGX30DF780C4 - Stratix II GX FPGA 33.8K LE FBGA-780 | Intel
EP2SGX30DF780C4 β End of LifeAltera
EP2SGX30DF780C4N
EP2SGX30DF780C4N - Stratix II GX 30K LEs FPGA 780-FBGA | Altera
EP2SGX30DF780C4N β Last Time BuySpecification Comparison
| Parameter | EP2SGX30DF780C4 | EP2SGX30DF780C4N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Eol | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $112.00 | $171.00 |
| Family | Stratix II GX | Stratix II GX |
| Logic Elements | 33,880 | β |
| Logic Cells | 33,880 | β |
| Number of LABs / CLBs | 1,694 | β |
| Total Number of I/Os | 361 | β |
| Maximum Operating Frequency | 717 MHz | β |
| Number of Transceivers | 20 (embedded multi-gigabit) | β |
| Core Voltage | 1.2 V | β |
| Package | FBGA-780 (780-FBGA, 29 x 29 mm, 1 mm pitch) | 780-FBGA (29 x 29 mm, 1.0 mm pitch) |
| Mounting Type | Surface Mount | Surface Mount (flip-chip BGA) |
| Process Technology | 90 nm CMOS | 90 nm CMOS |
| Operating Temperature Grade | Commercial (C4) | β |
| Programmable Terminals | BGA ball grid (780 terminals) | β |
| Package Code | BGA | β |
| Package Shape | Square | β |
| MSL Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| RoHS Status | Compliant (per manufacturer product page) | β |
| Lead-Free | Yes | β |
| Logic Elements (LEs) | β | 33,880 |
| Logic Array Blocks (LABs) | β | 1,694 |
| Total RAM Bits | β | 1,369,728 |
| User I/O Pins | β | 361 |
| Maximum Internal Frequency | β | 622 MHz |
| Core Supply Voltage | β | 1.15 V to 1.25 V |
| Operating Temperature | β | -40C to +85C |
| Lead-Free / RoHS | β | Lead-free (per FindIC datasheet) |
| Transceivers | β | [DATA_NEEDED: number of transceiver channels and per-channel data rate] |
| DSP Blocks | β | [DATA_NEEDED: DSP block count] |
| PLLs | β | [DATA_NEEDED: PLL count] |
| Configuration Method | β | SRAM (volatile, external flash required) |