EP3SE260F1517I4N vs EP3SE260F1517I4LN Comparison

Detailed side-by-side comparison of EP3SE260F1517I4N by Intel and EP3SE260F1517I4LN by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EP3SE260F1517I4N EP3SE260F1517I4N - Stratix III E FPGA, 255K LE, 1517-BGA | Intel

EP3SE260F1517I4N - Stratix III E FPGA, 255K LE, 1517-BGA | Intel

EP3SE260F1517I4N ⚠ Last Time Buy
Intel
EP3SE260F1517I4LN EP3SE260F1517I4LN - 260K LE Stratix III E FPGA, 1517-FCBGA | Intel

EP3SE260F1517I4LN - 260K LE Stratix III E FPGA, 1517-FCBGA | Intel

EP3SE260F1517I4LN ⚠ Last Time Buy

Specification Comparison

Parameter EP3SE260F1517I4N EP3SE260F1517I4LN
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $10,500.00 $2,895.00
Series Stratix III E β€”
Logic Elements 255,000 255,000
Embedded Memory Bits 16,672,768 bits 16,672,768 bits (~2,044 KBytes)
Embedded Memory (M9K/M144K blocks) [DATA_NEEDED: total Kbits and block count] β€”
User I/O Pins 976 β€”
Transceivers [DATA_NEEDED: number of full-duplex channels] Stratix III E family supports up to 24 transceivers up to 8.5 Gbps
Transceiver Data Rate 600 Mbps to 6.375 Gbps β€”
DSP Blocks [DATA_NEEDED: number of 18x18 multipliers] β€”
PLLs [DATA_NEEDED: total PLL count] β€”
Core Voltage 1.1 V β€”
Process Technology TSMC 65 nm 40 nm CMOS
Package 1517-BBGA, FCBGA 1517-ball FCBGA (40 mm x 40 mm, 1.0 mm pitch)
Package Body Size [DATA_NEEDED: mm x mm] β€”
Operating Temperature -40 Β°C to +100 Β°C (Industrial) -40C to +100C (case, industrial)
Operating Temperature Grade Industrial (I4) β€”
Mounting Type Surface Mount (BGA) β€”
Lead-Free / RoHS [DATA_NEEDED: explicit RoHS statement] Yes (N suffix)
MSL Level [DATA_NEEDED: MSL classification] β€”
Logic Array Blocks (LABs) β€” 10,200
User I/O Count β€” 976
Family β€” Stratix III E (Enhanced)
Speed Grade β€” I4 (industrial, 4th tier)
Power Option β€” L (low-power)
DSP Blocks (18x18 multipliers) β€” Up to 384 (family-level, device-specific count not in provided data)
Partial Reconfiguration β€” Supported
Memory Interface Support β€” DDR3, DDR2, QDR II+ (hardened PHY)
Configuration Scheme β€” Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP), JTAG

Datasheets & Resources

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