EP3SE260H780C2N vs EP3SE260H780C3N Comparison
Detailed side-by-side comparison of EP3SE260H780C2N by Intel and EP3SE260H780C3N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP3SE260H780C2N - Stratix III E FPGA 255K LE, 780-BGA | Intel
EP3SE260H780C2N โ Last Time BuyIntel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N โ ActiveSpecification Comparison
| Parameter | EP3SE260H780C2N | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3,600.00 | $1,325.00 |
| Series | Stratix III E | Stratixยฎ III E |
| Logic Elements | 255,000 | โ |
| LABs / CLBs | 10,200 | โ |
| Total RAM Bits | 16,672,768 | โ |
| User I/O Count | 488 | โ |
| Number of Transceivers | [DATA_NEEDED: transceiver count] | โ |
| Core Voltage | 0.9 V | โ |
| Package | 780-BGA FCBGA | 780-BBGA, FCBGA (H780) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | Commercial (0C to +85C) | โ |
| Speed Grade | C2 | โ |
| MSL Level | 3 (168 hours) | โ |
| Reflow Peak Time Max | 40 s | โ |
| RoHS Status | [DATA_NEEDED: rohs status] | Compliant (lead-free 'N' suffix) |
| Lead-Free | [DATA_NEEDED: lead-free] | โ |
| Package Code | BGA | โ |
| Terminal Form | Ball | โ |
| Number of Terminals | 780 | โ |
| Process Node | 40 nm | โ |
| Logic Elements (LE) | โ | 255,000 |
| Embedded Memory (bits) | โ | 16,672,768 |
| Number of LABs/CLBs | โ | 10,200 |
| User I/Os | โ | 488 |
| Number of Pins / Balls | โ | 780 |
| Operating Temperature | โ | 0 ยฐC to +85 ยฐC (C grade, commercial) |
| Process Technology | โ | 40 nm CMOS |
| Maximum Core Frequency | โ | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | โ | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | โ | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | โ | [DATA_NEEDED: number of DSP blocks and precision] |
| Moisture Sensitivity Level (MSL) | โ | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | โ | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | โ | Altera Quartus II (legacy); Intel Quartus Prime |