EP3SE260H780C2N vs EP3SE260H780C4LG Comparison
Detailed side-by-side comparison of EP3SE260H780C2N by Intel and EP3SE260H780C4LG by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP3SE260H780C2N - Stratix III E FPGA 255K LE, 780-BGA | Intel
EP3SE260H780C2N β Last Time BuyAltera
EP3SE260H780C4LG - Stratix III E FPGA, 488 I/O, 780-HBGA | Altera
EP3SE260H780C4LG β ActiveSpecification Comparison
| Parameter | EP3SE260H780C2N | EP3SE260H780C4LG |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $3,600.00 | $1,290.00 |
| Series | Stratix III E | β |
| Logic Elements | 255,000 | 254,400 |
| LABs / CLBs | 10,200 | β |
| Total RAM Bits | 16,672,768 | β |
| User I/O Count | 488 | β |
| Number of Transceivers | [DATA_NEEDED: transceiver count] | β |
| Core Voltage | 0.9 V | β |
| Package | 780-BGA FCBGA | 780-ball FineLine BGA (HBGA, 29 mm x 29 mm, 1.0 mm pitch) |
| Mounting Type | Surface Mount | Surface Mount (BGA) |
| Operating Temperature Range | Commercial (0C to +85C) | β |
| Speed Grade | C2 | C4 (commercial, mid-speed tier) |
| MSL Level | 3 (168 hours) | 3 (per JEDEC J-STD-020) |
| Reflow Peak Time Max | 40 s | β |
| RoHS Status | [DATA_NEEDED: rohs status] | Compliant (Pb-free HBGA) |
| Lead-Free | [DATA_NEEDED: lead-free] | β |
| Package Code | BGA | β |
| Terminal Form | Ball | β |
| Number of Terminals | 780 | β |
| Process Node | 40 nm | β |
| Family | β | Stratix III Enhanced (EP3SE) |
| Adaptive Logic Modules (ALMs) | β | 101,760 |
| Embedded Memory (M9K + M144K) | β | 18.36 Mbits |
| DSP Blocks (18-bit x 18-bit) | β | 768 |
| 18-bit x 18-bit Multipliers | β | 1,536 |
| Transceivers (full-duplex) | β | 8 (up to 6.375 Gbps) |
| Maximum User I/O Pins | β | 488 |
| Temperature Grade | β | Commercial (0C to +85C junction) |
| Process Technology | β | 65 nm TSMC low-power CMOS |
| Operating Voltage (Core) | β | 0.9 V / 1.0 V / 1.1 V (programmable) |
| External Memory Interface | β | Up to 800 Mbps DDR3, QDR II+, RLDRAM II |
| Hard IP Blocks | β | PCIe Gen2, 10GbE MAC, memory controllers |