EP3SL200H780C3N vs EP3SE260H780C3N Comparison
Detailed side-by-side comparison of EP3SL200H780C3N by Intel and EP3SE260H780C3N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N โ ActiveSpecification Comparison
| Parameter | EP3SL200H780C3N | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4,995.00 | $1,325.00 |
| Family | Stratix III L (low-power) | โ |
| Process Node | 40 nm | โ |
| Logic Elements | 200,000 | โ |
| Embedded Memory Bits | 10,901,504 bits | โ |
| Logic Array Blocks (LABs) | 8,000 | โ |
| User I/Os | 488 | 488 |
| Package | 780-Ball FCBGA (HBGA), 29 x 29 mm | 780-BBGA, FCBGA (H780) |
| Mounting Type | Surface Mount | Surface Mount |
| Maximum Internal Clock Frequency | 800 MHz | โ |
| Transceivers | 24 channels, up to 3.75 Gbps | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | 384 | [DATA_NEEDED: number of DSP blocks and precision] |
| Speed Grade | C3 (commercial, -3 speed) | โ |
| Operating Temperature | 0C to +85C (commercial) | 0 ยฐC to +85 ยฐC (C grade, commercial) |
| Voltage - Core | 0.9 V / 1.0 V (core, VCC) | โ |
| Voltage - I/O | 1.2 V to 3.3 V (VCCIO banks) | โ |
| MSL Level | 3 | โ |
| Lead-Free / RoHS | Yes | โ |
| Mounting Pitch | 1.0 mm ball pitch | โ |
| PLLs | 12 (Stratix III PLL array) | โ |
| Configuration | JTAG IEEE Std 1149.1, passive/active serial | โ |
| Series | โ | Stratixยฎ III E |
| Logic Elements (LE) | โ | 255,000 |
| Embedded Memory (bits) | โ | 16,672,768 |
| Number of LABs/CLBs | โ | 10,200 |
| Number of Pins / Balls | โ | 780 |
| Process Technology | โ | 40 nm CMOS |
| Maximum Core Frequency | โ | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | โ | [DATA_NEEDED: VCCINT nominal V] |
| RoHS Status | โ | Compliant (lead-free 'N' suffix) |
| Moisture Sensitivity Level (MSL) | โ | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | โ | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | โ | Altera Quartus II (legacy); Intel Quartus Prime |