EP3SL200H780I4LN vs EP3SL200H780C3N Comparison
Detailed side-by-side comparison of EP3SL200H780I4LN by Altera and EP3SL200H780C3N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP3SL200H780I4LN | EP3SL200H780C3N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $1,280.00 | $4,995.00 |
| Series | Stratix III L | β |
| Family | Stratix III L (Low-Power) | Stratix III L (low-power) |
| Manufacturer | Intel / Altera (now Intel PSG) | β |
| Number of Logic Elements / Cells | 200,000 | β |
| Number of LABs / CLBs | 8,000 | β |
| Total RAM Bits | 10,901,504 (approximately 10.9 Mbit) | β |
| Number of I/O | 488 | β |
| Voltage - Supply | 0.9 V core (selectable Vcore) | β |
| Operating Temperature | -40C to +100C (industrial) | 0C to +85C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| Package / Case | 780-BBGA, FCBGA (Flip-Chip BGA) | β |
| Process Technology | 65 nm CMOS | β |
| Speed Grade | I4 (Industrial, mid-speed grade) | C3 (commercial, -3 speed) |
| RoHS Status | RoHS Compliant (lead-free) | β |
| MSL Level | MSL 3 (168 Hours, per JEDEC J-STD-020) | 3 |
| Roaming Pin Name Suffix | LN = lead-free, industrial temp, H780 780-ball package | β |
| Process Node | β | 40 nm |
| Logic Elements | β | 200,000 |
| Embedded Memory Bits | β | 10,901,504 bits |
| Logic Array Blocks (LABs) | β | 8,000 |
| User I/Os | β | 488 |
| Package | β | 780-Ball FCBGA (HBGA), 29 x 29 mm |
| Maximum Internal Clock Frequency | β | 800 MHz |
| Transceivers | β | 24 channels, up to 3.75 Gbps |
| DSP Blocks | β | 384 |
| Voltage - Core | β | 0.9 V / 1.0 V (core, VCC) |
| Voltage - I/O | β | 1.2 V to 3.3 V (VCCIO banks) |
| Lead-Free / RoHS | β | Yes |
| Mounting Pitch | β | 1.0 mm ball pitch |
| PLLs | β | 12 (Stratix III PLL array) |
| Configuration | β | JTAG IEEE Std 1149.1, passive/active serial |