EP610DC-15 vs EP610IDC-15 Comparison
Detailed side-by-side comparison of EP610DC-15 by Altera and EP610IDC-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-15 | EP610IDC-15 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.95 | $9.95 |
| Product Family | Classic EPLD (EP610) | β |
| Architecture | UV-erasable CMOS PAL-type | β |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | β |
| Dedicated Inputs | 20 | β |
| Bidirectional I/O Pins | 16 | β |
| Total Product Terms | 160 | β |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 15 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0C to 70C (commercial) | 0C to +70C (commercial) |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CerDIP (ceramic DIP) |
| Mounting Type | Through-Hole | Through-hole |
| Programming Method | JEDEC fuse map, UV erasure | β |
| Technology | CMOS | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Device Family | β | Altera Classic EPLD |
| Usable Gates | β | 300 |
| Maximum Frequency | β | 66 MHz |
| Process Technology | β | CMOS, UV-erasable / OTP |
| I/O Pins | β | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | β | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | β | UV-erasable, OTP-compatible |
| Development Tool | β | MAX+PLUS II |
| Programming Current | β | 11.0 mA typical (per Classic family datasheet) |