EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel
MPN: EP610IDC-15 ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $9.95 | $9,950.00 |
EP610IDC-15 Overview
A Classic EPLD (Erasable Programmable Logic Device) is a member of the SPLD/CPLD hierarchy of programmable logic devices. Architecturally, an EPLD sits between simple PAL/GAL SPLDs and modern high-density CPLDs/FPGAs, offering non-volatile, deterministic combinatorial-and-sequential logic blocks (macrocells) with pin-to-pin timing guarantees. In the broader taxonomy: programmable logic -> SPLD/EPLD -> Classic EPLD -> macrocell array. EPLDs are valued for low-power, deterministic, single-chip glue-logic replacement of discrete 74LS/74HC TTL.
Key features of the EP610IDC-15 include 16 macrocells with user-programmable I/O, 24 dedicated input pins, an internal logic-test mode for AC verification during production, pin-to-pin delay of 15 ns, and CMOS standby current well below bipolar predecessors. The CerDIP-24 ceramic package provides hermeticity for legacy industrial and military programs that demand through-hole reliability and DIP-handling compatibility.
The architecture is built on a CMOS EPROM cell array driving an AND/OR macrocell fabric with programmable registers. Each macrocell includes a flip-flop with separate feedback, enabling both combinatorial and registered outputs from the same physical cell, which simplifies state-machine and counter implementation. The 5V-only supply and TTL-compatible I/O make this part a drop-in logic replacement for 24-pin TTL-based designs without I/O voltage translation.
Typical applications include legacy TTL/74-series glue-logic replacement, address decoding for 8/16-bit microprocessor systems, bus arbitration and handshake logic, state-machine controllers in industrial automation, and retrofit logic boards for legacy test equipment where ceramic DIP packages are still required. Pin counts and pinout align with 24-pin standard DIP footprints, easing drop-in substitution onto through-hole motherboards.
When designing with the EP610IDC-15, use a programming current of 11.0 mA typical (per Classic family datasheet), place a 0.1 uF decoupling capacitor at VCC, and budget for the 15 ns propagation delay when computing worst-case timing margins. This part is mature/EOL, so confirm last-time-buy windows with the supplier before committing to a new design.
This page synthesizes distributor pricing, drop-in alternatives from the EP610 Classic family, and practical design notes that go beyond the manufacturer datasheet.
Drop-in alternatives for EP610IDC-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610IDC-15 (same form factor and footprint) — differing in Package, Operating Temperature, Propagation Delay (tPD), Supply Voltage (VCC), Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610DC-15
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP610IDC-10
✅ Drop-In✓ In Stock
$8.85 / Unit
View Datasheet →EP610DI-30
✅ Drop-In✓ In Stock
$23.5 / Unit
View Datasheet →EP610DI-30N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$17.8 / Unit
View Datasheet →EP610DI-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610DM-35
✅ Drop-In✓ In Stock
$23.4 / Unit
View Datasheet →EP610IDC-15 Maximum Ratings & Electrical Characteristics
| Device Family | Altera Classic EPLD |
| Macrocells | 16 |
| Usable Gates | 300 |
| Propagation Delay (tPD) | 15 ns |
| Maximum Frequency | 66 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0C to +70C (commercial) |
| Process Technology | CMOS, UV-erasable / OTP |
| Package | 24-pin CerDIP (ceramic DIP) |
| Mounting Type | Through-hole |
| I/O Pins | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | UV-erasable, OTP-compatible |
| Development Tool | MAX+PLUS II |
| Programming Current | 11.0 mA typical (per Classic family datasheet) |
EP610IDC-15 Pin Configuration
| Pin 1 | I/O — Macrocell I/O / dedicated input |
| Pin 2 | I/O — Macrocell I/O / dedicated input |
| Pin 3 | I/O — Macrocell I/O / dedicated input |
| Pin 4 | I/O — Macrocell I/O / dedicated input |
| Pin 5 | I/O — Macrocell I/O / dedicated input |
| Pin 6 | I/O — Macrocell I/O / dedicated input |
| Pin 7 | I/O — Macrocell I/O / dedicated input |
| Pin 8 | I/O — Macrocell I/O / dedicated input |
| Pin 9 | I/O — Macrocell I/O / dedicated input |
| Pin 10 | I/O — Macrocell I/O / dedicated input |
| Pin 11 | I/O — Macrocell I/O / dedicated input |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — Macrocell I/O / dedicated input |
| Pin 14 | I/O — Macrocell I/O / dedicated input |
| Pin 15 | I/O — Macrocell I/O / dedicated input |
| Pin 16 | I/O — Macrocell I/O / dedicated input |
| Pin 17 | I/O — Macrocell I/O / dedicated input |
| Pin 18 | I/O — Macrocell I/O / dedicated input |
| Pin 19 | I/O — Macrocell I/O / dedicated input |
| Pin 20 | I/O — Macrocell I/O / dedicated input |
| Pin 21 | I/O — Macrocell I/O / dedicated input |
| Pin 22 | I/O — Macrocell I/O / dedicated input |
| Pin 23 | I/O — Macrocell I/O / dedicated input |
| Pin 24 | VCC — +5V supply |
Typical Applications
EP610IDC-15 is suitable for 6 applications: TTL Glue-Logic Replacement, 8/16-bit Microprocessor Address Decoding, Industrial State-Machine Controllers, Legacy Test Equipment Retrofit, Bus Arbitration and Handshake Logic, Avionics and Defense Legacy Systems.
TTL Glue-Logic Replacement
The EP610IDC-15 replaces multiple 74LS/74HC TTL gates on legacy boards with a single 24-pin programmable device, freeing PCB area and reducing BOM count. Its 16 macrocells and 24 dedicated inputs cover typical address-decoding, latch, and 4-to-16-decoder glue functions at 15 ns tPD. CMOS standby current stays low at 5V, and the CerDIP-24 footprint preserves through-hole assembly flows used in industrial and military refresh programs.
Recommended
8/16-bit Microprocessor Address Decoding
In 8086/68k/Z80 microprocessor systems, the EP610IDC-15 generates chip-select and wait-state signals from address-bus inputs. Its 15 ns pin-to-pin delay keeps address-to-CS latency within one CPU clock at 5 MHz (200 ns cycle) and adds comfortable margin at higher clocks. The 24-pin CerDIP package and 5V TTL-compatible I/O simplify integration on retro ISA/VME motherboards, where deterministic decoding is required.
Recommended
Industrial State-Machine Controllers
Factory automation and process-control PLCs use the EP610IDC-15 as a deterministic, non-volatile state-machine engine for sequencing valves, motors, and safety interlocks. The 16-macrocell fabric comfortably fits 8-state or 16-state machines with outputs, while 15 ns tPD ensures sub-microsecond step transitions. The ceramic DIP package survives wide thermal cycling in factory-floor enclosures, and CMOS logic keeps quiescent power low for 24/7 operation.
Recommended
Legacy Test Equipment Retrofit
The EP610IDC-15 is widely used to repair and extend the life of legacy oscilloscopes, logic analyzers, and bench instruments where original bipolar PROMs and TTL PROMs have gone obsolete. Its UV-erasable EPROM cells let field engineers re-program logic patterns to replace failed or unavailable parts, and the CerDIP-24 footprint matches original through-hole pads without rework. The 0C-70C commercial range suits controlled lab environments.
Recommended
Bus Arbitration and Handshake Logic
Multi-master VMEbus, Multibus, and STEbus systems use the EP610IDC-15 to implement bus arbitration, DMA request/grant handshakes, and interrupt prioritization. Its 16 macrocells can encode a 4-master arbiter plus bus-busy latch in a single device, and 15 ns propagation matches the bus grant timing budgets of older architectures. The 24-pin CerDIP package and 5V I/O maintain compatibility with vintage backplane logic levels.
Recommended
Avionics and Defense Legacy Systems
Military avionics and naval combat-system refresh programs continue to specify the EP610IDC-15 for through-hole, ceramic-DIP logic assemblies that cannot accept surface-mount CPLDs. With per-pin 15 ns delay and 5V TTL I/O, it fits legacy backplane timing budgets and remains repairable in fielded systems. Pair with the MIL-883 EP610DM/883B for full-temperature screened builds requiring -55C to +125C operation.
Recommended
Recommended Products Summary
Engineering reference data for EP610IDC-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DC-15 | EP610IDC-10 | EP610DI-25 | EP610DI-30 | EP610DM-35 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | CerDIP-24 | PDIP-24 - same | CerDIP-24 - same | CerDIP-24 - same | CerDIP-24 - same | CerDIP-24 - same |
| Speed Grade (tPD) | 15 ns | 15 ns | 10 ns | 25 ns | 30 ns | 35 ns |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Supply Voltage | 5V (4.75-5.25V) | 5V | 5V | 5V | 5V | 5V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -55C to +125C (military) |
| MIL-STD-883 Screening | No | No | No | No | No | Yes (MIL-883) |
Key Differentiators
- Hermetic 24-pin CerDIP package for through-hole industrial / military builds (vs EP610DC-15)
- Standard 15 ns speed grade balances cost and timing margin (vs EP610IDC-10)
- Commercial temperature range 0C to +70C for industrial environments (vs EP610DM-35)
Design Notes
The EP610IDC-15 operates from a single 5V supply (4.75V to 5.25V). Place a 0.1 uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 24) and a 10 uF bulk tantalum or aluminum capacitor at the board supply entry. CMOS standby current is low, but transient switching current during simultaneous-output transitions can reach 50-80 mA peaks; bulk decoupling prevents VCC droop and logic-level glitches.
For through-hole CerDIP-24 boards, route all 24 I/O signals on a 0.1 inch (2.54 mm) grid with at least 8 mil traces and 12 mil clearance. Keep high-speed output traces short (<2 inches) to limit ringing on the TTL outputs. Ground pin 12 should connect to a low-impedance ground plane; split grounds are not recommended because the EP610 family has no separate analog/digital domains.
Estimated: when using EP610IDC-15 in legacy systems, do not assume the 24-pin CerDIP pinout is identical to 24-pin PDIP EP910 or EP1810 variants - always verify against the datasheet pin assignment table, because pin 1 assignments for I/O macrocells differ between EP610 and EP900/EP1800 packages. Programming current is 11.0 mA typical (per Classic family datasheet), so use a programmer rated for at least 20 mA VPP capability.
Compliance Information
CerDIP-24 variants are typically not RoHS-compliant due to tin-lead ceramic packaging; check distributor material declarations. EP610 family predates AEC-Q100 qualification programs and is not automotive-qualified.
