EP610DC-20 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610DC-20 by Intel and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-20 | EP610DC-35 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.85 | $18.40 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | β |
| Family | Classic EP610 | Altera Classic EP610 |
| Logic Macrocells | 16 | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 16 (bidirectional) | β |
| Total Usable Pins | 20 | β |
| Product Terms (p-terms) | 160 | β |
| Propagation Delay (tPD) | 22 ns | 35 ns |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Programming Method | UV erasure + parallel programmer | β |
| Process Technology | CMOS, UV-erasable floating gate | CMOS |
| Mounting Type | Through-hole | Through-Hole (DIP) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Device Type | β | CPLD - Classic EPLD |
| Macrocells | β | 16 |
| Usable Gates | β | 300 |
| Maximum Frequency (fMAX) | β | 28.6 MHz |
| Pipelined Data Rate | β | up to 100 MHz |
| Program/erase Method | β | UV-erasable (windowed CERDIP) |
| Manufacturer | β | Originally Altera; today supplied via Rochester Electronics (authorized) |