EP610DC-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
MPN: EP610DC-35 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $30.91 | $30.91 |
| 10 | $28.5 | $285.00 |
| 100 | $24.75 | $2,475.00 |
| 500 | $21.2 | $10,600.00 |
| 1,000 | $18.4 | $18,400.00 |
EP610DC-35 Overview
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays with a programmable interconnect. CPLDs sit in the broader hierarchy of programmable logic: programmable logic device (PLD) -> CPLD -> programmable logic -> semiconductor. They are commonly used as "glue logic" to replace discrete 74-series TTL gates, state machines, address decoding, and bus interfacing in designs where an FPGA would be over-specified.
The EP610DC-35 features a UV-erasable quartz windowed CERDIP package, allowing the device to be erased with ultraviolet light and re-programmed many times - ideal for prototyping and design iteration. The CMOS Classic architecture provides bipolar-compatible speed at CMOS power levels, with deterministic timing that simplifies static timing analysis. Macrocell flip-flops and product-term sharing support both combinatorial and registered logic functions.
Typical applications include address decoding and interrupt generation in 8-bit and 16-bit microprocessor systems, bus arbitration and glue logic in industrial controller boards, state-machine-based peripheral controllers, and replacement of multiple discrete PAL/TTL packages. The 5V single-supply operation and 24-pin DIP form factor are convenient for legacy and through-hole designs.
When designing with the EP610DC-35, engineers should note that the part is mature/legacy silicon and is supplied today through Rochester Electronics as an authorized Altera/Intel foundry partner. Lead time and pricing should be confirmed at order entry. Use the Altera MAX+plus II or classic Altera programming tools with a compatible parallel-port programmer for device configuration.
This page synthesizes distributor pricing, authorized stocking-channel information, drop-in alternatives, and practical design notes for the EP610DC-35 - information not consolidated in the original Altera datasheet alone.
Drop-in alternatives for EP610DC-35 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610DC-35 (same form factor and footprint) β differing in Package, Operating Temperature, Propagation Delay (tPD), Family, Technology.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610DC-25
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP610DC-20
β Drop-Inβ In Stock
$15.85 / Unit
View Datasheet βEP610DC-15
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP610DC-10
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP610DC-30
β Drop-Inβ In Stock
$10.4 / Unit
View Datasheet βEP610DC-35 Maximum Ratings & Electrical Characteristics
| Device Type | CPLD - Classic EPLD |
| Family | Altera Classic EP610 |
| Macrocells | 16 |
| Usable Gates | 300 |
| Propagation Delay (tPD) | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz |
| Pipelined Data Rate | up to 100 MHz |
| Supply Voltage (VCC) | 5 V |
| Process Technology | CMOS |
| Program/erase Method | UV-erasable (windowed CERDIP) |
| Package | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Mounting Type | Through-Hole (DIP) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) |
EP610DC-35 Pin Configuration
| Pin 1 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 2 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 3 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 4 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 5 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 6 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 7 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 8 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 9 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 12 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 13 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 14 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 15 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 16 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 17 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 18 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 19 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 20 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 21 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 22 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 23 | I/O β Bidirectional I/O pin (macrocell-driven) |
| Pin 24 | VCC β +5V supply |
Typical Applications
EP610DC-35 is suitable for 6 applications: Address Decoding & Interrupt Glue Logic, Industrial Control State Machines, Bus Arbitration & Interface Bridging, Legacy PAL/TTL Replacement, Peripheral Controller (UART, Timer, Custom I/O), Prototype & Design Validation Platform.
Address Decoding & Interrupt Glue Logic
The EP610DC-35's 16 macrocells and 35 ns propagation delay make it a strong fit for address decoding in 8-bit and 16-bit microprocessor systems. Its 300 usable gates are more than enough to decode the full 64KB address space of an 8086 or 68000 system, while the deterministic tPD guarantees no glitches on chip-select lines during address transitions. Compared to discrete 74LS138/139 decoders, the EP610DC-35 replaces 3-5 packages with one, simplifying PCB layout. Place it on the local bus between the processor and peripheral array.
Recommended
Industrial Control State Machines
The EP610DC-35's macrocell flip-flops and product-term sharing support registered Moore and Mealy state machines for industrial sequencers. The 5V supply and 0-70C commercial temperature range suit factory-floor controller boards, and the 35 ns tPD gives plenty of margin for slow electromechanical actuators. The UV-erasable windowed CERDIP package allows design iteration on the production line. Use it to replace discrete 74LS-series state-machine implementations with a single reprogrammable part.
Recommended
Bus Arbitration & Interface Bridging
The EP610DC-35 handles bus arbitration logic between multiple masters on shared-address/data buses (e.g., DMA arbitration, dual-port RAM handshaking). Its 16 macrocells can encode multi-master priority schemes and bus-request/grant state machines in a single chip. The 35 ns propagation delay is adequate for 8 MHz bus cycles and the 5V I/O is directly compatible with TTL-level peripherals. Place it close to the bus transceivers to minimize stub length.
Recommended
Legacy PAL/TTL Replacement
The EP610DC-35 is functionally a 16-macrocell superset of older 20-pin PAL devices and can replace 2-4 standard PALs plus surrounding 74LS glue logic in legacy designs. Re-targeting older 20-pin PAL equations to the EP610DC-35 consolidates the BOM and improves reliability by removing socketed PALs. Designers use the Altera MAX+plus II legacy toolchain to import PAL fuse maps and recompile for the EP610 footprint.
Recommended
Peripheral Controller (UART, Timer, Custom I/O)
The EP610DC-35's macrocells and I/O count make it suitable for building custom peripheral controllers - small UARTs, timer/counter blocks, or proprietary serial protocols - that don't justify a full microcontroller. The deterministic tPD simplifies baud-rate generator design, and the registered macrocells implement transmit/receive shift registers cleanly. Use it as a co-processor alongside an 8051 or Z80 for I/O expansion in embedded boards.
Recommended
Prototype & Design Validation Platform
The EP610DC-35's UV-erasable windowed CERDIP package supports 100+ erase/reprogram cycles, making it ideal for prototype iteration. Engineers can compile, program, test in-circuit, erase under a UV lamp, and recompile - a fast development loop unavailable with OTP parts like the EP610PC-35. Use the EP610DC-35 in development sockets, then migrate to EP610PC-35 for production to reduce unit cost.
Recommended
Recommended Products Summary
Engineering reference data for EP610DC-35 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DC-25 | EP610DC-20 | EP610DC-15 | EP610DC-10 | EP610DC-30 |
|---|---|---|---|---|---|---|
| Package | CDIP-24 (windowed CERDIP) | CDIP-24 (windowed CERDIP) - same | CDIP-24 (windowed CERDIP) - same | CDIP-24 (windowed CERDIP) - same | CDIP-24 (windowed CERDIP) - same | CDIP-24 (windowed CERDIP) - same |
| Brand | Altera (supplied by Rochester Electronics) | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 35 ns | 25 ns (faster) | 20 ns (faster) | 15 ns (faster) | 10 ns (faster) | 30 ns (slightly faster) |
| Maximum Frequency (fMAX) | 28.6 MHz | 40 MHz | 50 MHz | 66.7 MHz | 100 MHz | 33 MHz |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Erasable / Windowed | Yes (UV-erasable CERDIP) | Yes (UV-erasable CERDIP) | Yes (UV-erasable CERDIP) | Yes (UV-erasable CERDIP) | Yes (UV-erasable CERDIP) | Yes (UV-erasable CERDIP) |
| Price (qty 100, USD) | 24.75 | higher (faster speed grade) | higher (faster speed grade) | higher (faster speed grade) | higher (faster speed grade) | similar (close speed grade) |
Key Differentiators
- Industry-standard Altera Classic EPLD, longest established supply channel (vs EP610DM-35 (different package))
- UV-erasable windowed CERDIP enables design iteration (vs EP610PC-35 (plastic OTP))
- Pin-compatible speed-grade upgrade path within same family (vs Modern CPLDs (e.g., MAX II, MAX V))
Design Notes
The EP610DC-35 operates from a single 5V Β±5% supply (4.75V to 5.25V). Place a 0.1uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 24) and a bulk 10-47uF tantalum or electrolytic capacitor on the supply rail near the device. ICC during static (un-programmed) operation is in the low-mA range; dynamic ICC rises with toggle frequency on the output pins. Use a star-ground topology to keep digital switching currents out of analog ground returns.
The 24-pin CERDIP-24 package has a 0.300-inch (7.62mm) row-to-row pin pitch with 0.100-inch (2.54mm) pin pitch - standard DIP. Provide a UV-transparent socket or a windowed CERDIP socket (e.g., Aries 24-pin low-profile) so the part can be erased and re-programmed without desoldering. If using a through-hole DIP socket, ensure the socket's retention force is adequate for the CERDIP's heavier ceramic body. Avoid running high-frequency signals adjacent to the analog-programming pins.
Common pitfalls when designing with the EP610DC-35: (1) Do not assume any macrocell pin is a dedicated input or output - all I/O pins are bidirectional and must be configured in the design file. (2) Programming requires a legacy Altera-compatible parallel-port programmer - USB-based modern programmers do NOT support the EP610 Classic family. (3) The 'DC' (windowed CERDIP) package must be erased under a UV lamp (wavelength 253.7nm, ~30 minutes exposure) before re-programming; programming without erasure is not supported. (4) For production builds, migrate to the EP610PC-35 (plastic OTP DIP) once the design is finalized to reduce cost.
Compliance Information
Compliance status not explicitly confirmed in retrieved web data. CERDIP packages with UV windows typically contain non-RoHS materials; verify with Rochester Electronics for specific compliance documentation. AEC-Q100 not applicable - this is a commercial-grade legacy logic device.
