EP610DC-20 vs EP610DI-35 Comparison
Detailed side-by-side comparison of EP610DC-20 by Intel and EP610DI-35 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 ObsoleteSpecification Comparison
| Parameter | EP610DC-20 | EP610DI-35 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.85 | $9.85 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | β |
| Family | Classic EP610 | Altera Classic EPLD |
| Logic Macrocells | 16 | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 16 (bidirectional) | 16 bidirectional |
| Total Usable Pins | 20 | β |
| Product Terms (p-terms) | 160 | β |
| Propagation Delay (tPD) | 22 ns | β |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) | [DATA_NEEDED: industrial/commercial grade range] |
| Package | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (Ceramic DIP) |
| Programming Method | UV erasure + parallel programmer | β |
| Process Technology | CMOS, UV-erasable floating gate | β |
| Mounting Type | Through-hole | Through-hole |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not confirmed in supplied web data] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Series | β | EP610 |
| Logic Cells / Macrocells | β | 16 macrocells |
| Usable Gates | β | 300 |
| Product Terms | β | 160 |
| Total Inputs | β | 20 (including 4 dedicated inputs) |
| Propagation Delay (tpd) | β | 35 ns |
| Maximum Toggle Frequency | β | 28.6 MHz |
| Internal Pipelined Data Rate | β | Up to 100 MHz |
| Supply Voltage | β | 5 V |
| Technology | β | CMOS, UV-erasable |