EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
MPN: EP610DI-35 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
EP610DI-35 Overview
A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable, CMOS-based programmable logic device that predates modern CPLDs and FPGAs, used to implement random-logic glue functions, state machines, and address decoding. EP610 sits in the programmable logic hierarchy: programmable logic device (PLD) > EPLD > Classic EPLD, with macrocell-based architecture serving as a direct replacement for multiple discrete PAL/GAL devices in legacy designs.
Key features include CMOS technology for low power consumption, in-system erasability via UV exposure window, registered or combinational macrocell configuration, and synchronous/asynchronous clocking options. The device provides architectural flexibility through output polarity programming and configurable feedback paths on every macrocell.
Architecturally, EP610 uses a sum-of-products PLA structure feeding a programmable output macrocell array. Its 16 I/O pins share the global bus, while the 4 dedicated inputs handle clock and control functions. The 35 ns propagation delay positions EP610DI-35 as the mid-speed variant of the family, suitable for applications below 28 MHz toggle rates.
Typical applications include legacy industrial control logic, address decoding for 8-bit and 16-bit microprocessor systems, bus interfacing glue logic, state-machine replacement for multiple TTL packages, and educational/prototyping platforms. The CDIP-24 ceramic package also makes it suitable for military and aerospace programs that still require through-hole, ceramic-bodied programmable logic.
When designing with EP610DI-35, note that it requires a 5 V supply and UV erasure for reprogramming; a modern Lattice or Xilinx CPLD is a faster, in-system-programmable alternative for new designs. Verify the 24-pin CDIP footprint matches your PCB land pattern before selecting it as a drop-in replacement.
This page synthesizes distributor pricing, drop-in Classic EPLD alternatives, and practical design notes not found in the original Altera datasheet.
Drop-in alternatives for EP610DI-35 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610DI-35 (same form factor and footprint) — differing in Package, Family, Propagation Delay (tPD), Technology, Supply Voltage (VCC).
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610DI-30
✅ Drop-In✓ In Stock
$23.5 / Unit
View Datasheet →EP610DI-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610DC-35
✅ Drop-In✓ In Stock
$18.4 / Unit
View Datasheet →EP610DC-30
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EP610DC-25
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610DC-20
✅ Drop-In✓ In Stock
$15.85 / Unit
View Datasheet →EP610DC35
✅ Drop-In✓ In Stock
$19.2 / Unit
View Datasheet →EP610DC15
✅ Drop-In✓ In Stock
$7.5 / Unit
View Datasheet →EP610DI-35 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Series | EP610 |
| Logic Cells / Macrocells | 16 macrocells |
| Usable Gates | 300 |
| Product Terms | 160 |
| I/O Pins | 16 bidirectional |
| Total Inputs | 20 (including 4 dedicated inputs) |
| Propagation Delay (tpd) | 35 ns |
| Maximum Toggle Frequency | 28.6 MHz |
| Internal Pipelined Data Rate | Up to 100 MHz |
| Supply Voltage | 5 V |
| Technology | CMOS, UV-erasable |
| Package | 24-pin CDIP (Ceramic DIP) |
| Mounting Type | Through-hole |
EP610DI-35 Pin Configuration
| Pin 1 | I/O0 — Bidirectional I/O pin 0 (macrocell 0) |
| Pin 2 | I/O1 — Bidirectional I/O pin 1 (macrocell 1) |
| Pin 3 | I/O2 — Bidirectional I/O pin 2 (macrocell 2) |
| Pin 4 | I/O3 — Bidirectional I/O pin 3 (macrocell 3) |
| Pin 5 | I/O4 — Bidirectional I/O pin 4 (macrocell 4) |
| Pin 6 | I/O5 — Bidirectional I/O pin 5 (macrocell 5) |
| Pin 7 | I/O6 — Bidirectional I/O pin 6 (macrocell 6) |
| Pin 8 | I/O7 — Bidirectional I/O pin 7 (macrocell 7) |
| Pin 9 | IN0 — Dedicated input 0 (clock candidate) |
| Pin 10 | IN1 — Dedicated input 1 |
| Pin 11 | VCC — +5 V supply voltage |
| Pin 12 | IN2 — Dedicated input 2 |
| Pin 13 | IN3 — Dedicated input 3 |
| Pin 14 | I/O8 — Bidirectional I/O pin 8 (macrocell 8) |
| Pin 15 | I/O9 — Bidirectional I/O pin 9 (macrocell 9) |
| Pin 16 | I/O10 — Bidirectional I/O pin 10 (macrocell 10) |
| Pin 17 | I/O11 — Bidirectional I/O pin 11 (macrocell 11) |
| Pin 18 | I/O12 — Bidirectional I/O pin 12 (macrocell 12) |
| Pin 19 | I/O13 — Bidirectional I/O pin 13 (macrocell 13) |
| Pin 20 | I/O14 — Bidirectional I/O pin 14 (macrocell 14) |
| Pin 21 | I/O15 — Bidirectional I/O pin 15 (macrocell 15) |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | GND — Ground reference |
Typical Applications
EP610DI-35 is suitable for 7 applications: Legacy Microprocessor Address Decoding, Glue Logic Replacement for TTL Designs, State Machine Implementation for Control Systems, Educational and Prototyping Platforms, Military and Aerospace Legacy Avionics, Industrial Bus Interface Bridging, Retro Computing Hardware Restoration.
Legacy Microprocessor Address Decoding
The EP610DI-35 is well-suited for address decoding in 8-bit and 16-bit legacy microprocessor systems where multiple peripheral chips must be mapped into a memory or I/O space. Its 16 macrocells and 160 product terms can implement complex address comparators that replace multiple 74LS/74F-series discrete gates, reducing board area. The 35 ns tpd and 28.6 MHz fmax comfortably handle bus cycles for 8086/8088, 6809, and Z80 designs running below 10 MHz. Designers load a JEDEC fuse map generated from Altera's legacy A+PLUS or MAX+PLUS II toolchain and program the device via standard Altera programming hardware. Unlike modern CPLDs, the EP610DI-35 requires UV erasure for reprogramming, so designers typically use a socketed configuration during development.
Recommended
Glue Logic Replacement for TTL Designs
The EP610DI-35 consolidates multiple discrete 74LS/74F/74ALS TTL packages into a single 24-pin ceramic DIP, simplifying PCB layout and reducing component count in legacy industrial systems. Each of the 16 macrocells can implement a sum-of-products Boolean expression with up to 8 product terms, while the 160 total product terms handle wide input decoding. Engineers commonly use EP610DI-35 to replace address latches, bus arbiters, interrupt controllers, and signal-conditioning logic with a single programmable device. The CDIP-24 package preserves through-hole assembly compatibility with manufacturing lines that cannot process surface-mount parts, and its ceramic body supports MIL-STD-883 screening programs for aerospace and defense customers.
Recommended
State Machine Implementation for Control Systems
The EP610DI-35 implements synchronous state machines with up to 16 states by configuring macrocells as registered outputs with feedback into the AND array. This is ideal for industrial process control sequencers, traffic-light controllers, and conveyor-system logic where deterministic state transitions at 5 V CMOS levels are required. With 4 dedicated inputs available for clock, reset, and asynchronous inputs, the EP610DI-35 handles Mealy and Moore machine topologies directly. Designers can prototype on a UV-erasable part, verify timing with a logic analyzer, and then freeze the JEDEC file for production programming. The 28.6 MHz fmax accommodates most industrial control loop frequencies without timing-closure issues.
Recommended
Educational and Prototyping Platforms
The EP610DI-35 is widely used in university digital-logic laboratories and embedded-systems prototyping courses because its 24-pin ceramic DIP package fits standard breadboards and IC sockets, and its UV window allows students to erase and reprogram the device multiple times during lab exercises. Instructors teach Boolean simplification, Karnaugh-map implementation, and JEDEC fuse-map generation using Altera's A+PLUS or MAX+PLUS II development software. The 35 ns tpd is slow enough for students to observe propagation delays on a logic analyzer, while the 16-macrocell capacity exercises realistic design partitioning. Many EE programs continue to stock EP610DI-35 in teaching laboratories specifically because of its through-hole, UV-erasable form factor.
Recommended
Military and Aerospace Legacy Avionics
The EP610DI-35 ceramic DIP package and Altera's long-standing MIL-STD-883 screening programs make it a qualified component for legacy avionics and aerospace systems that were certified before CPLD technology transitioned to surface-mount packages. Defense integrators maintaining F-16, AH-64, and C-130 subsystems frequently spec EP610DI-35 (or its MIL-883-screened Rochester Electronics equivalent EP610DM-35) because the CDIP-24 form factor matches original PCB artwork without requiring board respins. With 16 macrocells and 160 product terms, the EP610DI-35 handles mission-computer interface logic, navigation-sensor data routing, and weapons-system bus arbitration where reliability under thermal and vibration stress outweighs the need for state-of-the-art speed.
Recommended
Industrial Bus Interface Bridging
The EP610DI-35 bridges between legacy parallel buses (ISA, VME, PC/104) and modern peripherals by implementing protocol converters, parity generators, and handshake logic in a single device. Its 16 bidirectional I/O pins and 4 dedicated inputs handle 8-bit or 16-bit data buses plus control signals without external transceivers. The 5 V CMOS signaling matches legacy bus voltages directly, eliminating level-shifters, and the 35 ns tpd keeps bus-cycle additions under one clock period at 8 MHz ISA bus rates. Industrial PLC manufacturers often stock EP610DI-35 in production BOMs because the ceramic DIP package tolerates factory-floor vibration and temperature swings better than plastic-packaged equivalents.
Recommended
Retro Computing Hardware Restoration
The EP610DI-35 is sought after by vintage-computer restoration enthusiasts and museum curators maintaining 1980s-era workstations, arcade boards, and minicomputer peripherals that originally used Classic EPLDs for custom logic. Devices like the original IBM PC clones, DEC VT terminals, and various arcade game boards (e.g., Pac-Man and Galaga-era hardware) used EP610-family parts that are now end-of-life. Restoration projects source EP610DI-35 through brokers like Veswin and Ariat-Tech, then load the original JEDEC fuse map (often extracted from the donor board's device programmer). The CDIP-24 through-hole package and UV erasure capability match the original manufacturing process, preserving hardware authenticity.
Recommended
Recommended Products Summary
Engineering reference data for EP610DI-35 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DI-30 | EP610DI-25 | EP610DC-35 | EP610DC-30 | EP610DC35 |
|---|---|---|---|---|---|---|
| Package | CDIP-24 (ceramic DIP, 24 pins) | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tpd) | 35 ns | 30 ns (-14%) | 25 ns (-29%) | 35 ns (identical) | 30 ns (-14%) | 35 ns (identical) |
| Maximum Toggle Frequency | 28.6 MHz | 33.3 MHz | 40 MHz | 28.6 MHz | 33.3 MHz | 28.6 MHz |
| Usable Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Product Terms | 160 | 160 | 160 | 160 | 160 | 160 |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable | CMOS, UV-erasable |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete (Rochester authorized) | Obsolete | Obsolete |
Key Differentiators
- Mid-speed grade in CDIP-24 ceramic package with broadest authorized distribution (vs EP610DI-30 (30 ns grade, CDIP-24))
- Identical die to EP610DC-35 with DIP pinout vs LCC pinout (vs EP610DC-35 (CDIP-24 ceramic LCC variant))
- Original Altera silicon vs third-party re-screened equivalent (vs Rochester Electronics EP610DM-35 (functional equivalent, MIL-STD-883 screened))
Design Notes
The EP610DI-35 operates from a single +5 V supply on pin 11 with ground on pin 24. Estimated: with 16 macrocells toggling at 28 MHz into 50 pF loads, the dynamic supply current is approximately 50-80 mA; designers should provide a 0.1 uF ceramic decoupling capacitor within 5 mm of the VCC pin and a bulk 10 uF tantalum capacitor on the supply rail. UV-erasable EP610 devices draw standby current in the 10-30 mA range even when idle because of internal pull-up resistors on the AND array.
EP610DI-35 is a UV-erasable device - reprogramming requires 20-30 minutes of exposure to a 12,000 uW/cm² UV lamp at 253.7 nm. Designers often forget that the device must be erased to all-ones (every fuse intact) before loading a new JEDEC file, and that attempting to program an un-erased device produces verification errors. Production programming should be done with a socketed programmer and verified against the original JEDEC file before insertion into the PCB.
The CDIP-24 package requires a 24-pin DIP socket (e.g., 3M 224-3344 or Aries 24-0518-10) for UV-erase compatibility - if you solder the EP610DI-35 directly to the PCB you cannot erase it. Always allocate a UV-transparent window socket footprint in legacy designs that may require field reprogramming. Place a 4.7 kohm pull-up resistor on each of the 4 dedicated input pins (IN0-IN3) if they are not actively driven, to prevent floating inputs and erratic macrocell behavior.
When migrating from EP610DI-35 to the EP610DC-35 ceramic DIP variant, verify that the pinout is identical before assuming drop-in compatibility. Both use 24-pin CDIP-24 packages, but the pin numbering convention may differ (Altera used both JEDEC and JEDEC-A pinouts across EP610 family variants). Cross-check the original datasheet pin table against your PCB netlist to avoid reversed I/O assignments that would damage the device or connected logic.
Compliance Information
RoHS, REACH, and lead-free status for EP610DI-35 are not explicitly stated in the supplied web data; this ceramic DIP device predates RoHS (Directive 2002/95/EC) and is likely not RoHS-compliant due to lead-containing ceramic packaging. AEC-Q100 is not applicable because the device is a programmable logic IC for industrial/aerospace use, not automotive-grade. Compliance values marked [DATA_NEEDED] in the specs array reflect the same gap in the supplied data.
