EP610DC-25 vs EP610DC-30 Comparison
Detailed side-by-side comparison of EP610DC-25 by Rochester Electronics and EP610DC-30 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β Active
Specification Comparison
| Parameter | EP610DC-25 | EP610DC-30 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $10.40 |
| Family | Altera Classic EPLD | EP610 (Classic Device Family) |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | β |
| Maximum Propagation Delay (tPD) | 25 ns | β |
| Pipelined Data Rate | Up to 100 MHz | β |
| Number of I/O Pins | 22 | β |
| Number of Dedicated Inputs | 4 | β |
| Total Pin Count | 24 | β |
| Package | 24-pin CDIP (Ceramic DIP, through-hole) | 24-pin CERDIP (windowed) |
| Mounting Type | Through Hole | Through-Hole |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | β |
| Operating Temperature | 0 C to +70 C | Commercial (0C to +70C) |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM |
| Programming Method | JEDEC fuse-map / UV-erase | β |
| Speed Grade Suffix | -25 (25 ns tPD) | β |
| Logic Expanders | β | 4 (4 product terms per macrocell) |
| Usable Gates | β | 300 |
| Maximum Pipelined Clock Frequency | β | 100 MHz |
| Propagation Delay (tPD) | β | 30 ns |
| Dedicated Inputs | β | 16 |
| I/O Pins | β | 16 (with output enable) |
| Speed Grade | β | -30 (30 ns tPD) |
| Programmability | β | UV-erasable, windowed EPROM |
| Security Bit | β | Yes (protects design after programming) |
| Output Modes | β | Registered and Combinatorial |