EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
MPN: EP610DC-25 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
EP610DC-25 Overview
A Classic EPLD (Erasable Programmable Logic Device) is a type of early-generation programmable logic IC that combines the high integration of a PLD with the erasable, reprogrammable nature of UV-erasable CMOS logic. EPLDs sit within the broader programmable logic hierarchy: PLD -> CPLD (Complex PLD) / EPLD -> FPGA. The Classic family targets glue-logic, decode, and state-machine applications where a small number of logic equations must be implemented with deterministic, TTL-equivalent timing.
Key specifications include a maximum tPD of 25 ns, 22 user I/O pins, 4 dedicated input pins (24 pins total minus VCC/GND), 16 macrocells, 300 equivalent gates, an internal supply voltage of 4.75 V to 5.25 V (5 V nominal), and a commercial operating temperature range of 0 C to +70 C. The -DC- suffix indicates the ceramic DIP package, while the -25 speed grade indicates the 25 ns tPD timing bin.
Architecturally, the EP610 uses a sum-of-products AND/OR array feeding 16 output macrocells with programmable output polarity and feedback paths, allowing combinatorial and registered logic to be implemented in a single device. The CMOS EPROM technology gives the part zero standby current when not being read, while the macrocell flip-flops provide synchronous register-based state-machine support. With pipelined data rates to 100 MHz, the EP610DC-25 is suitable for high-speed decoder, address-decode, and bus-arbitration roles in legacy 5 V systems.
Typical applications include bus decode and address decoding in 5 V microprocessor systems, glue logic in industrial controllers, state-machine controllers for instrumentation, and pin-compatible logic replacement for legacy designs where the original Altera Classic EPLD must be renewed. The 24-pin DIP form factor is also favored for breadboarding and educational platforms. When designing with the EP610DC-25, ensure the design is implemented in legacy Altera Classic EPLD design tools or compatible JEDEC fuse-map programming software, as modern Quartus software does not support the Classic family.
Drop-in alternatives for EP610DC-25 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610DC-25 (same form factor and footprint) — differing in Package, Operating Temperature, Propagation Delay (tPD), Family, Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610DC-20
✅ Drop-In✓ In Stock
$15.85 / Unit
View Datasheet →EP610DC-15
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP610DC-10
✅ Drop-In✓ In Stock
$7.95 / Unit
View Datasheet →EP610DM-35
✅ Drop-In✓ In Stock
$23.4 / Unit
View Datasheet →EP610DC-30
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EP610DC-25 Maximum Ratings & Electrical Characteristics
| Family | Altera Classic EPLD |
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 16 |
| Equivalent Gates | 300 |
| Maximum Propagation Delay (tPD) | 25 ns |
| Pipelined Data Rate | Up to 100 MHz |
| Number of I/O Pins | 22 |
| Number of Dedicated Inputs | 4 |
| Total Pin Count | 24 |
| Package | 24-pin CDIP (Ceramic DIP, through-hole) |
| Mounting Type | Through Hole |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0 C to +70 C |
| Technology | CMOS EPROM (UV-erasable) |
| Programming Method | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | -25 (25 ns tPD) |
EP610DC-25 Pin Configuration
| Pin 1 | I/O0 — Bidirectional I/O pin 0 |
| Pin 2 | I/O1 — Bidirectional I/O pin 1 |
| Pin 3 | I/O2 — Bidirectional I/O pin 2 |
| Pin 4 | I/O3 — Bidirectional I/O pin 3 |
| Pin 5 | I/O4 — Bidirectional I/O pin 4 |
| Pin 6 | I/O5 — Bidirectional I/O pin 5 |
| Pin 7 | I/O6 — Bidirectional I/O pin 6 |
| Pin 8 | I/O7 — Bidirectional I/O pin 7 |
| Pin 9 | I/O8 — Bidirectional I/O pin 8 |
| Pin 10 | I/O9 — Bidirectional I/O pin 9 |
| Pin 11 | I/O10 — Bidirectional I/O pin 10 |
| Pin 12 | GND — Ground (0 V) |
| Pin 13 | I/O11 — Bidirectional I/O pin 11 |
| Pin 14 | I/O12 — Bidirectional I/O pin 12 |
| Pin 15 | I/O13 — Bidirectional I/O pin 13 |
| Pin 16 | I/O14 — Bidirectional I/O pin 14 |
| Pin 17 | I/O15 — Bidirectional I/O pin 15 |
| Pin 18 | I/O16 — Bidirectional I/O pin 16 |
| Pin 19 | I/O17 — Bidirectional I/O pin 17 |
| Pin 20 | I/O18 — Bidirectional I/O pin 18 |
| Pin 21 | I/O19 — Bidirectional I/O pin 19 |
| Pin 22 | I/O20 — Bidirectional I/O pin 20 |
| Pin 23 | I/O21 — Bidirectional I/O pin 21 / dedicated input |
| Pin 24 | VCC — Positive supply (5 V nominal) |
Typical Applications
EP610DC-25 is suitable for 6 applications: 5 V Bus Address Decoding, Industrial Glue Logic and State Machines, Pin-Compatible Logic Replacement, Test and Measurement Instrumentation, Legacy Telecom Line-Card Logic, Educational and Hobbyist Digital-Logic Platforms.
5 V Bus Address Decoding
The EP610DC-25 is widely used for 5 V microprocessor bus address decoding in legacy 8086, 68000, and Z80 systems. Its 16 macrocells and 22 I/O pins comfortably hold large multi-way chip-select decode trees while the 25 ns tPD comfortably fits within a single 8 MHz 8086 memory-access cycle. The DIP-24 footprint simplifies through-hole prototyping and field-replacement on industrial backplanes. Drop-in compatibility with EP610DC-20 lets designers tighten timing margin if a faster host bus is later selected.
Recommended
Industrial Glue Logic and State Machines
The EP610DC-25 integrates combinatorial decode plus registered state-machine logic in a single 24-pin DIP, replacing four to six discrete 74LS/74HC TTL packages on legacy industrial controllers. The CMOS EPROM technology provides zero standby current when the controller is idle, while the 100 MHz pipelined data rate handles synchronous register-based sequencing at full industrial-clock frequencies. Designers targeting industrial obsolescence-avoidance rely on Rochester Electronics' authorized continuation-of-supply for multi-decade program longevity.
Recommended
Pin-Compatible Logic Replacement
When a legacy Altera Classic EPLD must be renewed without a PCB redesign, the EP610DC-25 is the canonical 25 ns speed-grade option. Designers have access to EP610DC-10, -15, -20, -25, -30, and -35 bins in the identical CDIP-24 package, providing six timing options on a single PCB layout. The 0 C to +70 C commercial temperature range suits indoor industrial, telecom, and instrumentation enclosures, while the ceramic DIP body adds mechanical robustness for vibration-prone environments.
Recommended
Test and Measurement Instrumentation
Test-and-measurement front-ends often use the EP610DC-25 to implement custom trigger, gating, and pulse-train logic that does not fit a stock PAL or GAL. The 25 ns tPD gives clean, deterministic timing for pulse generation, while the 16 macrocells provide ample headroom for state-machine-based sequencer logic. The 24-pin DIP form factor is breadboard-friendly for laboratory prototyping, and Rochester Electronics' long-life-cycle support protects instruments that ship into 15- to 20-year service contracts.
Recommended
Legacy Telecom Line-Card Logic
Central-office telecom line cards that predate modern CPLDs often rely on Classic EPLDs for multiplexer, alarm, and supervision logic. The EP610DC-25's 5 V supply, 22 I/O pins, and CMOS EPROM technology match the original line-card power and logic budgets, while the CDIP-24 ceramic-DIP body tolerates the elevated temperatures inside telecommunications racks. Rochester Electronics' authorized-supply position keeps the line-card bill-of-materials stable for installed-base support and incremental capacity expansions.
Recommended
Educational and Hobbyist Digital-Logic Platforms
The EP610DC-25 in DIP-24 is a staple of university digital-logic labs and hobbyist retro-computing projects because it can be programmed with classic MAX+PLUS II or PALASM toolchains and erased under a UV lamp. Students learn sum-of-products AND/OR arrays, macrocell feedback paths, and JEDEC fuse-map generation on a forgiving through-hole footprint that survives repeated insertion into solderless breadboards. The 25 ns tPD is more than sufficient for teaching sequential-state-machine and decoder-design fundamentals.
Recommended
Recommended Products Summary
Engineering reference data for EP610DC-25 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DC-20 | EP610DC-15 | EP610DC-10 | EP610DM-35 | EP610DC-30 |
|---|---|---|---|---|---|---|
| Brand | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics | Rochester Electronics |
| Package | 24-pin CDIP | 24-pin CDIP - same | 24-pin CDIP - same | 24-pin CDIP - same | 24-pin CDIP - same | 24-pin CDIP - same |
| Maximum tPD | 25 ns | 20 ns (faster) | 15 ns (faster) | 10 ns (fastest) | 35 ns (slower) | 30 ns (slower) |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Equivalent Gates | 300 | 300 | 300 | 300 | 300 | 300 |
| User I/O Pins | 22 | 22 | 22 | 22 | 22 | 22 |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Operating Temperature | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C | 0 C to +70 C |
Key Differentiators
- Authorized continuation-of-supply via Rochester Electronics (vs EP610DC-25 from non-authorized brokers)
- Ceramic DIP-24 hermetic package (vs EP610PC-25 (plastic PDIP))
- 25 ns tPD - the legacy default speed grade (vs EP610DC-10 (10 ns tPD))
Design Notes
The EP610DC-25 belongs to the legacy Altera Classic EPLD family and is NOT supported by modern Intel Quartus Prime design software. Designers must use legacy Altera MAX+PLUS II, AHDL, or PALASM toolchains to generate the JEDEC fuse map. Programming requires a Classic-EPLD-compatible programmer; attempting to program the device with a MAX-II/MAX-V programmer will fail. If the original design source files are lost, the device can be read back with the legacy programmer and the JEDEC map can be archived for future re-sourcing.
Place a 0.1 uF decoupling capacitor as close as possible to the EP610DC-25 VCC pin (pin 24) and a bulk 10 uF electrolytic on the 5 V rail within 1 inch of the device. The 16-macrocell AND/OR array can produce fast sub-10 ns internal edge rates; keep all 22 I/O traces short and route clock inputs away from output switching lines to minimize ground-bounce-induced false-clocking. The DIP-24 footprint allows through-hole sockets to be used for in-circuit reprogramming during development.
Estimated: The EP610DC-25 in ceramic DIP-24 has a typical theta_JA of approximately 60 C/W for a still-air socketed installation. At maximum 5.25 V supply and a fully-loaded 16-macrocell design switching at 25 MHz with all 22 I/Os driving 50 pF loads, total power dissipation is approximately 250 mW, yielding a junction-temperature rise of 15 C above ambient. For high-density fully-populated designs, verify junction temperature against the 0 C to +70 C commercial limit. The ceramic DIP body tolerates higher ambient temperatures than plastic DIP, which is one reason it remains specified for industrial and military environments.
Compliance Information
The EP610DC-25 is a legacy Altera Classic EPLD packaged in a ceramic DIP (CDIP-24) that historically contains lead-bearing ceramic glass frit at the package-ceramic interface - it is commonly NOT RoHS-compliant in its original CDIP form. The Rochester Electronics product page does not explicitly state current RoHS/REACH compliance status; for RoHS-compliant designs, consider the EP610PC-25 plastic PDIP variant if available, or migrate to a modern Altera MAX II CPLD. AEC-Q100 qualification is not applicable because the part is not marketed for new automotive programs.
