EP610DC-30 vs EP610DC-10 Comparison
Detailed side-by-side comparison of EP610DC-30 by Altera and EP610DC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-30 | EP610DC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $7.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | β |
| Family | EP610 (Classic Device Family) | β |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 (4 product terms per macrocell) | β |
| Usable Gates | 300 | β |
| Maximum Pipelined Clock Frequency | 100 MHz | β |
| Propagation Delay (tPD) | 30 ns | β |
| Dedicated Inputs | 16 | β |
| I/O Pins | 16 (with output enable) | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Package | 24-pin CERDIP (windowed) | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Through-Hole | Through-Hole |
| Speed Grade | -30 (30 ns tPD) | -10 |
| Technology | CMOS EPROM | CMOS, EPROM-based (UV-erasable) |
| Programmability | UV-erasable, windowed EPROM | β |
| Security Bit | Yes (protects design after programming) | β |
| Output Modes | Registered and Combinatorial | β |
| Operating Temperature | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Device Family | β | Altera Classic EPLD |
| Maximum Pipelined Data Rate | β | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | β | 10 ns |
| Supply Voltage | β | 5 V (single supply) |
| Logic Elements | β | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | β | UV-erasable EPROM |
| Reprogrammable | β | Yes (UV erase window on package) |
| RoHS Status | β | [DATA_NEEDED: not stated in verified web data] |