EP610DC-10 - 16-Macrocell Classic EPLD, 10ns, 24-Pin CDIP | Intel
MPN: EP610DC-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $15.75 | $157.50 |
| 100 | $12.4 | $1,240.00 |
| 500 | $9.85 | $4,925.00 |
| 1,000 | $7.95 | $7,950.00 |
EP610DC-10 Overview
What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits between simple PAL/GAL devices and modern CPLDs/FPGAs in the PLD hierarchy: PLD -> EPLD -> CPLD -> FPGA -> programmable logic -> semiconductor. EPLDs use non-volatile EEPROM or EPROM storage to retain configuration at power-off, and provide predictable combinational and registered logic with deterministic timing - ideal for replacing multiple SSI/MSI discrete logic gates in a single package.
Key features of the EP610DC-10 include 16 macrocells, 24 I/O pins in the CDIP-24 windowed-ceramic package, 100 MHz pipelined throughput, and a propagation delay of 10 ns at the commercial temperature range. The Classic architecture provides a programmable AND/OR array feeding 16 output macrocells, each containing a programmable flip-flop for synchronous logic. EPROM-based configuration allows unlimited reprogramming when the device is erased under UV light through the quartz window on the top of the ceramic package.
The EP610DC-10's 24-pin ceramic DIP is windowed (erasable) and uses through-hole mounting, suitable for prototype, lab, and legacy industrial systems. The 'DC' suffix indicates the CDIP-24 ceramic DIP package, while '-10' denotes the 10 ns speed grade. The device requires a single 5V supply and supports TTL-compatible I/O.
Applications include legacy industrial control, address decoding, state machines, and bus-interface glue logic in older computer and telecom designs. Designers should note the ceramic DIP package requires through-hole PCB mounting and a UV eraser for reprogramming. This EP610DC-10 is an obsolete/EOL part; sourcing is limited to the secondary market, and modern alternatives should be evaluated for new designs.
Drop-in alternatives for EP610DC-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610DC-10 (same form factor and footprint) β differing in Package, Operating Temperature, Propagation Delay (tPD), Technology, Family.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EP610DC-25
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEP610DC-15
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEP610DC-35
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$18.4 / Unit
View Datasheet βEP610PC-10
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EP610PC-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$17.5 / Unit
View Datasheet βEP610DC-10 Maximum Ratings & Electrical Characteristics
| Device Family | Altera Classic EPLD |
| Macrocells | 16 |
| Maximum Pipelined Data Rate | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | 10 ns |
| Speed Grade | -10 |
| Package | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Through-Hole |
| Technology | CMOS, EPROM-based (UV-erasable) |
| Supply Voltage | 5 V (single supply) |
| Operating Temperature | 0C to +70C (commercial) |
| Logic Elements | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | UV-erasable EPROM |
| Reprogrammable | Yes (UV erase window on package) |
EP610DC-10 Pin Configuration
| Pin 1 | I/O β Programmable I/O pin / macrocell input |
| Pin 2 | I/O β Programmable I/O pin / macrocell input |
| Pin 3 | I/O β Programmable I/O pin / macrocell input |
| Pin 4 | I/O β Programmable I/O pin / macrocell input |
| Pin 5 | I/O β Programmable I/O pin / macrocell input |
| Pin 6 | I/O β Programmable I/O pin / macrocell input |
| Pin 7 | I/O β Programmable I/O pin / macrocell input |
| Pin 8 | I/O β Programmable I/O pin / macrocell input |
| Pin 9 | I/O β Programmable I/O pin / macrocell input |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β Programmable I/O pin / macrocell input |
| Pin 12 | I/O β Programmable I/O pin / macrocell input |
| Pin 13 | I/O β Programmable I/O pin / macrocell input |
| Pin 14 | I/O β Programmable I/O pin / macrocell input |
| Pin 15 | I/O β Programmable I/O pin / macrocell input |
| Pin 16 | I/O β Programmable I/O pin / macrocell input |
| Pin 17 | I/O β Programmable I/O pin / macrocell input |
| Pin 18 | I/O β Programmable I/O pin / macrocell input |
| Pin 19 | I/O β Programmable I/O pin / macrocell input |
| Pin 20 | I/O β Programmable I/O pin / macrocell input |
| Pin 21 | I/O β Programmable I/O pin / macrocell input |
| Pin 22 | I/O β Programmable I/O pin / macrocell input |
| Pin 23 | I/O β Programmable I/O pin / macrocell input |
| Pin 24 | VCC β +5V power supply |
Typical Applications
EP610DC-10 is suitable for 7 applications: Legacy Industrial Control Logic, Address Decoding and Bus Interfacing, State Machine Controllers, Glue Logic Integration, Legacy Telecom Backplane Interface, Prototype and Educational Use, Vintage Computer Restoration.
Legacy Industrial Control Logic
The EP610DC-10's 16 macrocells and 10 ns propagation delay make it suitable for legacy industrial control boards where the part was originally designed in. Its UV-erasable EPROM and 5V TTL-compatible I/O allow direct interfacing with 74-series logic and optocouplers. The deterministic timing simplifies safety-critical state-machine design. Its ceramic DIP package is rugged against vibration and thermal cycling in factory environments.
Recommended
Address Decoding and Bus Interfacing
The EP610DC-10's 16 macrocells and fast 10 ns delay are ideal for address decoding and bus-interface glue between microprocessors, memory, and peripherals. It can replace multiple 74LS138/139 decoders and PAL devices with one part, saving PCB area. The 5V TTL I/O directly interfaces with 8086, 68k, and other 5V buses. Deterministic combinational delay avoids bus-contention glitches.
Recommended
State Machine Controllers
The EP610DC-10's 16 macrocells each include a programmable flip-flop, providing ample register resources for Moore and Mealy state machines. The 100 MHz pipelined data rate and 10 ns delay support high-speed control loops in instrumentation. EPROM-based configuration ensures the state machine boots instantly at power-on without external memory. UV erasure allows rapid iteration during development.
Recommended
Glue Logic Integration
The EP610DC-10 consolidates multiple SSI/MSI gates - AND, OR, NAND, flip-flops, counters - into one programmable part, reducing board space and improving reliability. Its 24-pin CDIP footprint replaces 4-6 standard 74LS packages, simplifying PCB layout. The ceramic package withstands harsh environments and long-term thermal stress. Reprogrammability lets designers iterate without board rework.
Recommended
Legacy Telecom Backplane Interface
The EP610DC-10 was widely deployed in telecom backplanes for T1/E1 line interface cards and multiplexer designs. Its TTL-compatible I/O interfaces directly with bus transceivers and framer ICs of the era. The 100 MHz pipelined data rate handles high-speed serial protocol framing. Obsolescence makes this part a candidate for last-time-buy reserves in legacy telecom systems.
Recommended
Prototype and Educational Use
The EP610DC-10 is widely used in university EE labs and hobbyist retro-computing projects because of its UV-erasable windowed ceramic DIP and breadboard-friendly through-hole pins. Students learn EPLD design with the original Altera Classic tools. Hobbyists use it to recreate vintage computer glue from the 1980s. Availability on the secondary market keeps these educational and restoration projects feasible.
Recommended
Vintage Computer Restoration
The EP610DC-10 was used in original 1980s personal computers, peripherals, and arcade boards as glue logic. Restoration projects sourcing NOS (new old stock) parts rely on the secondary market for authentic replacements. Its UV-erasable ceramic DIP matches the original through-hole assembly. Modern CPLDs in different packages cannot be substituted without redesigning the vintage board.
Recommended
Recommended Products Summary
Engineering reference data for EP610DC-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610DC-25 | EP610DC-15 | EP610DC-35 | EP610PC-10 | EP610PC-15 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | CDIP-24 (windowed ceramic DIP) | CDIP-24 - same | CDIP-24 - same | CDIP-24 - same | PDIP-24 (plastic, non-windowed) | PDIP-24 (plastic, non-windowed) |
| Macrocells | 16 | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tpd) | 10 ns | 25 ns (slower) | 15 ns (slightly slower) | 35 ns (much slower) | 10 ns (same) | 15 ns (slightly slower) |
| Configuration Memory | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | UV-erasable EPROM | One-time-programmable EPROM (no UV window) | One-time-programmable EPROM (no UV window) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Faster speed grade in CDIP-24 package (vs EP610DC-25)
- UV-erasable and reprogrammable (vs EP610PC-10)
- Ceramic DIP ruggedness for harsh environments (vs EP610PC-10)
Design Notes
The EP610DC-10 uses a 24-pin ceramic DIP (CDIP-24) with through-hole pins on 2.54 mm (0.1 in) pitch. When laying out, reserve sufficient clearance around the package top because the quartz UV-erase window protrudes above the ceramic body. Use sockets (machined-pin DIP-24) for development boards to allow easy removal for UV erasure and reprogramming. For production runs, the one-time-programmable EP610PC-10 variant is preferred to reduce handling.
Estimated: At 5V VCC and typical 5 mA active ICC for the EP610DC-10, power dissipation is roughly 25 mW. Add a 100 nF ceramic decoupling capacitor as close as possible to the VCC pin (pin 24), plus a 10 uF bulk capacitor near the device. The classic CMOS EPROM technology has low static power but switching current spikes during macrocell transitions; place bypass caps to suppress noise on the 5V rail.
Do not confuse the EP610DC-10 with the EP610PC-10: the 'DC' suffix denotes a windowed ceramic DIP (UV-erasable, reprogrammable), while 'PC' is a plastic DIP (one-time-programmable, non-windowed). Both share the 24-pin DIP footprint but the PC variant cannot be UV-erased. Also, do not exceed 7V absolute maximum on VCC or expose the device to ESD above 2000V HBM without protection - Classic CMOS EPLDs are ESD-sensitive by modern standards.
The 10 ns tpd of the EP610DC-10 corresponds to roughly 100 MHz maximum toggle rate per output. When designing high-speed state machines, calculate worst-case combinational paths and ensure they fit within the 10 ns budget, including interconnect delay. The TTL-compatible outputs can drive 10-20 LS-TTL loads but use external buffers (74LS244) for bus-driving applications to avoid ground-bounce and signal-integrity issues.
Compliance Information
RoHS/REACH compliance status not stated in verified web data. The EP610DC-10 is an obsolete part from the late 1980s/early 1990s and pre-dates modern RoHS/REACH regulations. AEC-Q100 is not applicable for this legacy commercial-grade EPLD.
