EP610DC-35 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610DC-35 by Altera and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DC-35 | EP610DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $18.40 | $7.95 |
| Device Type | CPLD - Classic EPLD | β |
| Family | Altera Classic EP610 | β |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | β |
| Propagation Delay (tPD) | 35 ns | 15 ns (speed grade -15) |
| Maximum Frequency (fMAX) | 28.6 MHz | β |
| Pipelined Data Rate | up to 100 MHz | β |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Process Technology | CMOS | β |
| Program/erase Method | UV-erasable (windowed CERDIP) | β |
| Package | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Mounting Type | Through-Hole (DIP) | Through-Hole |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | 0C to 70C (commercial) |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | β |
| RoHS Status | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | [DATA_NEEDED: RoHS status] |
| Product Family | β | Classic EPLD (EP610) |
| Architecture | β | UV-erasable CMOS PAL-type |
| Logic Expanders | β | 4 |
| Dedicated Inputs | β | 20 |
| Bidirectional I/O Pins | β | 16 |
| Total Product Terms | β | 160 |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| Programming Method | β | JEDEC fuse map, UV erasure |
| Technology | β | CMOS |