EP610DI-25 vs EP610IDC-15 Comparison
Detailed side-by-side comparison of EP610DI-25 by Intel and EP610IDC-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-25 | EP610IDC-15 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $9.95 |
| Part Family | Classic EPLD | β |
| Macrocells | 16 | 16 |
| Propagation Delay (tPD) | 25 ns | 15 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | β |
| I/O Pins | 16 (bidirectional) | 24 (per package; macrocell-programmable) |
| Dedicated Inputs | 4 | β |
| Total User I/O | 20 | β |
| Technology | CMOS EPROM (UV-erasable) | β |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V (5 V nominal) |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | β |
| Pin Count | 24 | β |
| Mounting Type | Through-Hole (DIP) | Through-hole |
| Operating Temperature | Industrial (per "I" suffix) | 0C to +70C (commercial) |
| Speed Grade Suffix | 25 = 25 ns | β |
| Compliance | RoHS status unknown (legacy 1990s part) | β |
| Device Family | β | Altera Classic EPLD |
| Usable Gates | β | 300 |
| Maximum Frequency | β | 66 MHz |
| Process Technology | β | CMOS, UV-erasable / OTP |
| Package | β | 24-pin CerDIP (ceramic DIP) |
| Logic-Block Architecture | β | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | β | UV-erasable, OTP-compatible |
| Development Tool | β | MAX+PLUS II |
| RoHS Status | β | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Programming Current | β | 11.0 mA typical (per Classic family datasheet) |