EP610DI-30N vs EP610IDC-15 Comparison
Detailed side-by-side comparison of EP610DI-30N by Altera and EP610IDC-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610DI-30N | EP610IDC-15 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.80 | $9.95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | β |
| Family | Altera Classic EP610 | β |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 15 ns |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | 66 MHz |
| Supply Voltage (VCC) | 5 V Β±5% | 4.75 V to 5.25 V (5 V nominal) |
| Package | CDIP-24 (Ceramic DIP, windowed) | 24-pin CerDIP (ceramic DIP) |
| Pin Count | 24 | β |
| Operating Temperature | -40Β°C to +85Β°C (industrial) | 0C to +70C (commercial) |
| Process Technology | CMOS | CMOS, UV-erasable / OTP |
| Programming Method | UV-erasable (windowed ceramic) | β |
| Mounting Type | Through-hole (DIP) | Through-hole |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Device Family | β | Altera Classic EPLD |
| I/O Pins | β | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | β | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | β | UV-erasable, OTP-compatible |
| Development Tool | β | MAX+PLUS II |
| Programming Current | β | 11.0 mA typical (per Classic family datasheet) |