EP610IDC-10 vs EP610DC-25 Comparison
Detailed side-by-side comparison of EP610IDC-10 by Intel and EP610DC-25 by Rochester Electronics. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 β ActiveSpecification Comparison
| Parameter | EP610IDC-10 | EP610DC-25 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.85 | $9.95 |
| Device Family | Altera Classic EPLD | β |
| Logic Capacity | 300 usable gates | β |
| Macrocell Count | 16 macrocells | β |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | β |
| Maximum Counter Frequency (fCNT) | 100 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Compatibility | 100% TTL emulation | β |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS EPROM (UV-erasable) |
| Package Type | 24-pin Ceramic DIP (CDIP) | β |
| Dedicated Inputs | 4 | β |
| I/O Pins | 20 | β |
| Operating Temperature Range | 0 Β°C to +70 Β°C (commercial) | β |
| Programmable Interconnect | Yes (on-chip) | β |
| In-System Programmability | Yes (via MAX+PLUS II) | β |
| Boundary-Scan Test | Yes (per device documentation) | β |
| RoHS Status | [DATA_NEEDED: RoHS status of CDIP-10 variant] | β |
| Mounting Type | Through-hole | Through Hole |
| Family | β | Altera Classic EPLD |
| Product Type | β | EPLD (Erasable Programmable Logic Device) |
| Macrocells | β | 16 |
| Equivalent Gates | β | 300 |
| Maximum Propagation Delay (tPD) | β | 25 ns |
| Pipelined Data Rate | β | Up to 100 MHz |
| Number of I/O Pins | β | 22 |
| Number of Dedicated Inputs | β | 4 |
| Total Pin Count | β | 24 |
| Package | β | 24-pin CDIP (Ceramic DIP, through-hole) |
| Operating Temperature | β | 0 C to +70 C |
| Programming Method | β | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | β | -25 (25 ns tPD) |