EP610IDC-10 vs EP610IDC-15 Comparison

Detailed side-by-side comparison of EP610IDC-10 by Intel and EP610IDC-15 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610IDC-10 EP610IDC-15
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $8.85 $9.95
Device Family Altera Classic EPLD Altera Classic EPLD
Logic Capacity 300 usable gates β€”
Macrocell Count 16 macrocells β€”
Pin-to-Pin Logic Delay (tpd) 10 ns β€”
Maximum Counter Frequency (fCNT) 100 MHz β€”
Supply Voltage (VCC) 5 V (nominal) 4.75 V to 5.25 V (5 V nominal)
I/O Logic Compatibility 100% TTL emulation β€”
Technology CMOS, UV-erasable (windowed ceramic) β€”
Package Type 24-pin Ceramic DIP (CDIP) β€”
Dedicated Inputs 4 β€”
I/O Pins 20 24 (per package; macrocell-programmable)
Operating Temperature Range 0 Β°C to +70 Β°C (commercial) β€”
Programmable Interconnect Yes (on-chip) β€”
In-System Programmability Yes (via MAX+PLUS II) β€”
Boundary-Scan Test Yes (per device documentation) β€”
RoHS Status [DATA_NEEDED: RoHS status of CDIP-10 variant] [DATA_NEEDED: RoHS status of CerDIP variant]
Mounting Type Through-hole Through-hole
Macrocells β€” 16
Usable Gates β€” 300
Propagation Delay (tPD) β€” 15 ns
Maximum Frequency β€” 66 MHz
Operating Temperature β€” 0C to +70C (commercial)
Process Technology β€” CMOS, UV-erasable / OTP
Package β€” 24-pin CerDIP (ceramic DIP)
Logic-Block Architecture β€” AND/OR macrocell array with programmable flip-flops
Program/Erase β€” UV-erasable, OTP-compatible
Development Tool β€” MAX+PLUS II
Programming Current β€” 11.0 mA typical (per Classic family datasheet)

Datasheets & Resources

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