EP610IDC-10 vs EP610ILC10 Comparison
Detailed side-by-side comparison of EP610IDC-10 by Intel and EP610ILC10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IDC-10 | EP610ILC10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.85 | $4.10 |
| Device Family | Altera Classic EPLD | β |
| Logic Capacity | 300 usable gates | β |
| Macrocell Count | 16 macrocells | β |
| Pin-to-Pin Logic Delay (tpd) | 10 ns | β |
| Maximum Counter Frequency (fCNT) | 100 MHz | β |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V |
| I/O Logic Compatibility | 100% TTL emulation | β |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS, UV-erasable / OTP |
| Package Type | 24-pin Ceramic DIP (CDIP) | β |
| Dedicated Inputs | 4 | 4 |
| I/O Pins | 20 | β |
| Operating Temperature Range | 0 Β°C to +70 Β°C (commercial) | β |
| Programmable Interconnect | Yes (on-chip) | β |
| In-System Programmability | Yes (via MAX+PLUS II) | β |
| Boundary-Scan Test | Yes (per device documentation) | β |
| RoHS Status | [DATA_NEEDED: RoHS status of CDIP-10 variant] | Unknown - verify with manufacturer |
| Mounting Type | Through-hole | Surface Mount / Socket |
| Family | β | Classic EPLD (EP610) |
| Logic Elements | β | 16 macrocells |
| Gates | β | 300 gates equivalent |
| Product Terms | β | 160 |
| I/O Lines | β | 16 |
| Propagation Delay (tPD) | β | 15 ns (10 ns speed grade) |
| Maximum Internal Frequency | β | 100 MHz |
| Operating Temperature | β | -40 C to +85 C (Industrial) |
| Architecture | β | PAL-type AND-OR-NOT |
| Package | β | 28-pin PLCC (J-Lead) |