EP610ILC10 - 16-Macrocell Classic EPLD, 10ns PLCC-28 | Intel
MPN: EP610ILC10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.95 | $8.95 |
| 10 | $7.85 | $78.50 |
| 100 | $6.4 | $640.00 |
| 500 | $5.2 | $2,600.00 |
| 1,000 | $4.1 | $4,100.00 |
EP610ILC10 Overview
A CPLD/EPLD is a non-volatile programmable logic device that retains its configuration without external memory and provides fast, deterministic propagation delays. Within the broader hierarchy, the EP610 sits as: programmable logic -> PLD -> EPLD -> Classic EPLD. It is implemented in CMOS technology, offering low static power consumption compared to bipolar PAL alternatives, and supports both UV-erasable and one-time-programmable (OTP) operation.
Key features include 16 macrocells with 16 I/O lines and 4 dedicated inputs, 160 product terms, a 15ns pin-to-pin propagation delay (tPD), and a 100 MHz maximum internal clock frequency. The PAL-type AND-OR-NOT architecture with user-configurable macrocell flip-flops allows implementation of registered or combinatorial logic. The I-suffix indicates the industrial operating temperature range of -40C to +85C.
The EP610ILC10 uses a classic sum-of-products architecture with a programmable AND array feeding fixed OR terms, followed by individually configurable output macrocells. Each macrocell contains a flip-flop and programmable output polarity, supporting D, T, JK, and SR flip-flop modes. The device is programmed via the Altera programming algorithm using a master programming unit, with security bit support to protect design IP.
Typical applications include address decoding for microprocessor systems, bus interface glue logic, state-machine replacement, peripheral control, and 5V industrial control boards. The 100 MHz performance makes it useful in video timing and data-path control where fast, predictable logic is needed.
When designing, note that the EP610 is a mature, NRND/EOL part - verify lifetime-buy status with the distributor before committing to new designs. The 28-pin PLCC package requires a through-hole or socketed footprint, so plan board layout accordingly.
This page synthesizes distributor pricing, Classic EPLD family variants, and practical 5V glue-logic design notes not found in the original datasheet.
Drop-in alternatives for EP610ILC10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with EP610ILC10 (same form factor and footprint) — differing in Mounting Type, Package, Supply Voltage (VCC), I/O Pins, Device Family.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EP610ILC-25
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EP610IDC-10
✅ Drop-In✓ In Stock
$8.85 / Unit
View Datasheet →EP610ILC-10
✅ Drop-In✓ In Stock
$7.2 / Unit
View Datasheet →EP610IDC-15
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EP610ILC10
✅ Drop-In✓ In Stock
$4.1 / Unit
View Datasheet →EP610ILC10 Maximum Ratings & Electrical Characteristics
| Family | Classic EPLD (EP610) |
| Logic Elements | 16 macrocells |
| Gates | 300 gates equivalent |
| Product Terms | 160 |
| I/O Lines | 16 |
| Dedicated Inputs | 4 |
| Propagation Delay (tPD) | 15 ns (10 ns speed grade) |
| Maximum Internal Frequency | 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Operating Temperature | -40 C to +85 C (Industrial) |
| Technology | CMOS, UV-erasable / OTP |
| Architecture | PAL-type AND-OR-NOT |
| Package | 28-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount / Socket |
| RoHS Status | Unknown - verify with manufacturer |
EP610ILC10 Pin Configuration
| Pin 1 | I/O — Bidirectional I/O pin (macrocell 0) |
| Pin 2 | I/O — Bidirectional I/O pin (macrocell 1) |
| Pin 3 | I/O — Bidirectional I/O pin (macrocell 2) |
| Pin 4 | I/O — Bidirectional I/O pin (macrocell 3) |
| Pin 5 | I/O — Bidirectional I/O pin (macrocell 4) |
| Pin 6 | I/O — Bidirectional I/O pin (macrocell 5) |
| Pin 7 | I/O — Bidirectional I/O pin (macrocell 6) |
| Pin 8 | I/O — Bidirectional I/O pin (macrocell 7) |
| Pin 9 | I/O — Bidirectional I/O pin (macrocell 8) |
| Pin 10 | I/O — Bidirectional I/O pin (macrocell 9) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — Bidirectional I/O pin (macrocell 10) |
| Pin 13 | I/O — Bidirectional I/O pin (macrocell 11) |
| Pin 14 | I/O — Bidirectional I/O pin (macrocell 12) |
| Pin 15 | I/O — Bidirectional I/O pin (macrocell 13) |
| Pin 16 | I/O — Bidirectional I/O pin (macrocell 14) |
| Pin 17 | I/O — Bidirectional I/O pin (macrocell 15) |
| Pin 18 | IN — Dedicated input |
| Pin 19 | IN — Dedicated input |
| Pin 20 | IN — Dedicated input |
| Pin 21 | IN — Dedicated input |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | NC — Not connected (per datasheet) |
| Pin 25 | NC — Not connected (per datasheet) |
| Pin 26 | NC — Not connected (per datasheet) |
| Pin 27 | NC — Not connected (per datasheet) |
| Pin 28 | VCC — +5V power supply |
Typical Applications
EP610ILC10 is suitable for 7 applications: Microprocessor Address Decoding, Bus Interface Glue Logic, Industrial State-Machine Replacement, Legacy Peripheral Control, VME / Multibus Backplane Logic, Test Equipment and Lab Instrumentation, Telecom Line-Card Glue Logic.
Microprocessor Address Decoding
The EP610ILC10 is well-suited for 5V microprocessor address-decoding applications because its 16 macrocells provide ample product terms to decode up to 16 chip-select signals from a 24-bit address bus. With 10ns tPD and 100 MHz fMAX, the device adds negligible wait-state insertion for 33 MHz 80386 or 40 MHz 68030 designs. The 28-pin PLCC footprint allows the decoder to be placed adjacent to the CPU socket, and the PAL-type AND-OR architecture maps directly to traditional fusemap decoder equations. Industrial temperature range and 5V TTL-compatible I/O are ideal for ISA, VME, and embedded PC/104 bus decoding.
Recommended
Bus Interface Glue Logic
For bus-interface glue-logic functions such as bus arbitration, wait-state generation, and protocol translation, the EP610ILC10 replaces 4-7 discrete 22V10 PALs with a single 28-pin device. The 16-macrocell architecture provides enough product terms for typical bus-controller state machines, and the 10ns propagation delay comfortably meets ISA bus and 8 MHz STD-bus timing budgets. CMOS technology reduces power consumption versus bipolar PALs, while the security bit protects proprietary bus-protocol IP. The PLCC package can be socketed during development for quick logic iteration.
Recommended
Industrial State-Machine Replacement
The EP610ILC10 is widely used in industrial control applications to replace discrete 74LS-series state machines with a single reprogrammable device. Each macrocell supports D, T, JK, or SR flip-flop modes, allowing direct synthesis of Mealy or Moore machines for conveyor control, valve sequencing, and machine-tool logic. Industrial temperature grade (-40C to +85C) and 5V supply operation match legacy PLC and motor-drive backplanes. The 16 macrocells comfortably handle 4-8 state machines of moderate complexity, and UV-erasable windowed packages support field re-programming.
Recommended
Legacy Peripheral Control
Legacy peripheral control functions such as floppy-disk controllers, ISA sound cards, and parallel-port interfaces used the EP610ILC10 to consolidate timing generators, FIFO flag logic, and DMA handshake sequencers. The 100 MHz fMAX supports floppy data-separator and VGA pixel-clock generation, while the 16 I/O lines handle bidirectional data buses. The 28-pin PLCC fits inside the original 22V10 socket footprint with minor trace adjustments. NRND status means new designs should migrate to MAX II or MAX V, but existing peripherals still source this part for repair.
Recommended
VME / Multibus Backplane Logic
The EP610ILC10 is well-matched to VMEbus and Multibus backplane applications where 5V supply and TTL-compatible I/O are mandatory. Its 10ns tPD meets VMEbus DTACK and BERR timing requirements, and the 16 dedicated I/O plus 4 dedicated inputs handle the full VME address/data/control pin subset required for slave-only decoder logic. The PAL-type AND-OR array allows direct translation of existing ABEL or CUPL decoder equations without re-synthesis. Industrial temperature grade ensures operation in chassis with restricted airflow.
Recommended
Test Equipment and Lab Instrumentation
For test equipment, logic analyzers, and lab instrumentation, the EP610ILC10 provides deterministic 10ns timing for custom timing generators, trigger sequencers, and pulse-pattern decoders. The 100 MHz internal frequency supports pattern generation up to 50 MHz with registered outputs, and the security bit protects proprietary test sequences. UV-erasable windowed packages (JEDEC-standard ceramic windowed PLCC) allow in-house reprogramming during prototype iteration. The device is widely supported by classic programming tools such as Altera MAX+plus II baseline and Data I/O programmers.
Recommended
Telecom Line-Card Glue Logic
Telecom line cards and central-office equipment standardized on 5V Classic EPLDs in the 1990s, and the EP610ILC10 remains in service for T1/E1 framer control, HDLC channel assignment, and alarm-monitoring logic. Its 5V TTL I/O directly interfaces to legacy framing chips without level shifters, and the 10ns tPD meets channel-associated signalling timing. Industrial temperature grade and 30+ year Altera/Intel long-term-support history make it acceptable for NEBS-compliant telecom chassis. NRND status drives migration to MAX V EPM5V240 in new line-card designs.
Recommended
Recommended Products Summary
Engineering reference data for EP610ILC10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP610ILC-25 | EP610IDC-10 | EP610ILC-10 | EP610IDC-15 |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | PLCC-28 | PLCC-28 - same | PLCC-28 - same | PLCC-28 - same | PLCC-28 - same |
| Macrocells | 16 | 16 | 16 | 16 | 16 |
| Propagation Delay (tPD) | 15 ns | 25 ns (slower) | 15 ns | 15 ns | 20 ns |
| Maximum Frequency | 100 MHz | 83.3 MHz | 100 MHz | 100 MHz | 83.3 MHz |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) |
| Product Terms | 160 | 160 | 160 | 160 | 160 |
Key Differentiators
- Fastest 10ns speed grade in the EP610 Classic EPLD family (vs EP610ILC-25)
- Industrial temperature range in PLCC package (vs EP610DC-25 (DIP package))
- 16 macrocells with PAL-type AND-OR architecture (vs ATF22V10C (Atmel 22V10))
Design Notes
The EP610ILC10 operates from a single 5V supply (4.75V to 5.25V). Place a 0.1uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 28) and a 10uF tantalum bulk capacitor near the device. Estimated: at 100 MHz fMAX and typical 16-macrocell utilization, CMOS ICC is approximately 50-100 mA - the bulk capacitor prevents VCC sag during simultaneous macrocell switching. Tie the NC pins (22-27) directly to GND or leave floating per datasheet; they are not connected internally.
Use a PLCC-28 socket (e.g. 3M 28-pin or Aries 28-pin) during development to allow UV-erasable windowed-package reprogramming. The PLCC footprint requires a 1.27 mm pitch land pattern with rectangular SMD pads (approx 1.0 x 1.7 mm). Keep I/O traces short (< 50 mm) to minimize transmission-line effects at 100 MHz - the EP610 does not include input hysteresis on TTL inputs, so add an external Schmitt trigger (74LS14) on clock and asynchronous inputs if noise margin is marginal.
Estimated: When migrating from 22V10 PALs to the EP610ILC10, remember that the EP610 has 4 dedicated inputs in addition to the 16 I/O lines - the 22V10 only has 12 inputs plus 10 I/O, so unused EP610 inputs must be tied to a defined logic level (not floating) to prevent shoot-through current. The EP610 security bit is one-time programmable - once set, the JEDEC fuse map cannot be read back, so always archive the original programming file. Avoid mixing EP610 and 5V-tolerant MAX 7000S devices on the same JTAG chain - they use different programming algorithms.
Compliance Information
RoHS/lead-free status not confirmed in available web data - request manufacturer compliance certificate before use in RoHS-required designs. NRND status supersedes AEC-Q100 qualification concerns.
