EP610IDC-15 vs EP610DC-15 Comparison
Detailed side-by-side comparison of EP610IDC-15 by Intel and EP610DC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610IDC-15 | EP610DC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $7.95 |
| Device Family | Altera Classic EPLD | β |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | β |
| Propagation Delay (tPD) | 15 ns | 15 ns (speed grade -15) |
| Maximum Frequency | 66 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Operating Temperature | 0C to +70C (commercial) | 0C to 70C (commercial) |
| Process Technology | CMOS, UV-erasable / OTP | β |
| Package | 24-pin CerDIP (ceramic DIP) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Mounting Type | Through-hole | Through-Hole |
| I/O Pins | 24 (per package; macrocell-programmable) | β |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | β |
| Program/Erase | UV-erasable, OTP-compatible | β |
| Development Tool | MAX+PLUS II | β |
| RoHS Status | [DATA_NEEDED: RoHS status of CerDIP variant] | [DATA_NEEDED: RoHS status] |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | β |
| Product Family | β | Classic EPLD (EP610) |
| Architecture | β | UV-erasable CMOS PAL-type |
| Logic Expanders | β | 4 |
| Dedicated Inputs | β | 20 |
| Bidirectional I/O Pins | β | 16 |
| Total Product Terms | β | 160 |
| Maximum Internal Clock Frequency | β | 71.4 MHz |
| Programming Method | β | JEDEC fuse map, UV erasure |
| Technology | β | CMOS |