EP610IDC-15 vs EP610IDC-10 Comparison

Detailed side-by-side comparison of EP610IDC-15 by Intel and EP610IDC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EP610IDC-15 EP610IDC-10
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last_time_buy Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.95 $8.85
Device Family Altera Classic EPLD Altera Classic EPLD
Macrocells 16 β€”
Usable Gates 300 β€”
Propagation Delay (tPD) 15 ns β€”
Maximum Frequency 66 MHz β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (nominal)
Operating Temperature 0C to +70C (commercial) β€”
Process Technology CMOS, UV-erasable / OTP β€”
Package 24-pin CerDIP (ceramic DIP) β€”
Mounting Type Through-hole Through-hole
I/O Pins 24 (per package; macrocell-programmable) 20
Logic-Block Architecture AND/OR macrocell array with programmable flip-flops β€”
Program/Erase UV-erasable, OTP-compatible β€”
Development Tool MAX+PLUS II β€”
RoHS Status [DATA_NEEDED: RoHS status of CerDIP variant] [DATA_NEEDED: RoHS status of CDIP-10 variant]
Programming Current 11.0 mA typical (per Classic family datasheet) β€”
Logic Capacity β€” 300 usable gates
Macrocell Count β€” 16 macrocells
Pin-to-Pin Logic Delay (tpd) β€” 10 ns
Maximum Counter Frequency (fCNT) β€” 100 MHz
I/O Logic Compatibility β€” 100% TTL emulation
Technology β€” CMOS, UV-erasable (windowed ceramic)
Package Type β€” 24-pin Ceramic DIP (CDIP)
Dedicated Inputs β€” 4
Operating Temperature Range β€” 0 Β°C to +70 Β°C (commercial)
Programmable Interconnect β€” Yes (on-chip)
In-System Programmability β€” Yes (via MAX+PLUS II)
Boundary-Scan Test β€” Yes (per device documentation)

Datasheets & Resources

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