EP610ILC-10 vs EP610DC-10 Comparison
Detailed side-by-side comparison of EP610ILC-10 by Altera and EP610DC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC-10 | EP610DC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.20 | $7.95 |
| Device Family | Classic EPLD | Altera Classic EPLD |
| Product Type | UV-Erasable / OTP PLD | β |
| Architecture | PAL-type with macrocells | β |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | β |
| Product Terms | 160 | β |
| I/O Pins | 16 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Dedicated Inputs | 4 | β |
| Supply Voltage | 5 V (single supply) | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | β |
| Counter Frequency (fCNT) | 100 MHz | β |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | β |
| Package | PLCC-28 (plastic J-lead chip carrier) | 24-pin CDIP (Ceramic DIP, windowed) |
| Mounting Type | Surface Mount (PLCC socket or solder) | Through-Hole |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified web data] |
| Maximum Pipelined Data Rate | β | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | β | 10 ns |
| Speed Grade | β | -10 |
| Technology | β | CMOS, EPROM-based (UV-erasable) |
| Logic Elements | β | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | β | UV-erasable EPROM |
| Reprogrammable | β | Yes (UV erase window on package) |