EP610ILC-25 vs EP610DC-35 Comparison
Detailed side-by-side comparison of EP610ILC-25 by Altera and EP610DC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC-25 | EP610DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $18.40 |
| Family | Classic EPLD (EP610 series) | Altera Classic EP610 |
| Device Type | EEPLD (Electrically Erasable PLD) | CPLD - Classic EPLD |
| Usable Gates | 300 | 300 |
| Macrocells | 16 | 16 |
| Product Terms | 160 | β |
| Maximum Operating Frequency (fMAX) | 40 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Nominal Supply Voltage | 5 V | β |
| Total Inputs | 20 | β |
| Dedicated Inputs | 4 | β |
| Bidirectional I/O Pins | 16 | β |
| Operating Temperature Range | 0 C to +70 C (commercial) | β |
| Package | 28-pin PLCC (J-lead) | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Mounting Type | Surface Mount | Through-Hole (DIP) |
| Process Technology | CMOS, electrically erasable | CMOS |
| Programming Method | In-system, electrically erasable | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Propagation Delay (tPD) | β | 35 ns |
| Maximum Frequency (fMAX) | β | 28.6 MHz |
| Pipelined Data Rate | β | up to 100 MHz |
| Program/erase Method | β | UV-erasable (windowed CERDIP) |
| Operating Temperature | β | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Manufacturer | β | Originally Altera; today supplied via Rochester Electronics (authorized) |