EP610ILC-25 vs EP610ILC10 Comparison
Detailed side-by-side comparison of EP610ILC-25 by Altera and EP610ILC10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP610ILC-25 | EP610ILC10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $4.10 |
| Family | Classic EPLD (EP610 series) | Classic EPLD (EP610) |
| Device Type | EEPLD (Electrically Erasable PLD) | β |
| Usable Gates | 300 | β |
| Macrocells | 16 | β |
| Product Terms | 160 | 160 |
| Maximum Operating Frequency (fMAX) | 40 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Nominal Supply Voltage | 5 V | β |
| Total Inputs | 20 | β |
| Dedicated Inputs | 4 | 4 |
| Bidirectional I/O Pins | 16 | β |
| Operating Temperature Range | 0 C to +70 C (commercial) | β |
| Package | 28-pin PLCC (J-lead) | 28-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount | Surface Mount / Socket |
| Process Technology | CMOS, electrically erasable | β |
| Programming Method | In-system, electrically erasable | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | Unknown - verify with manufacturer |
| Logic Elements | β | 16 macrocells |
| Gates | β | 300 gates equivalent |
| I/O Lines | β | 16 |
| Propagation Delay (tPD) | β | 15 ns (10 ns speed grade) |
| Maximum Internal Frequency | β | 100 MHz |
| Operating Temperature | β | -40 C to +85 C (Industrial) |
| Technology | β | CMOS, UV-erasable / OTP |
| Architecture | β | PAL-type AND-OR-NOT |